1 // Copyright © 2019 Intel Corporation 2 // 3 // SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause 4 // 5 // Copyright © 2020, Microsoft Corporation 6 // 7 // Copyright 2018-2019 CrowdStrike, Inc. 8 // 9 // 10 use crate::arch::x86::{ 11 CpuIdEntry, DescriptorTable, FpuState, LapicState, MsrEntry, SegmentRegister, SpecialRegisters, 12 }; 13 use serde::{Deserialize, Serialize}; 14 use std::fmt; 15 16 pub mod emulator; 17 18 /// 19 /// Export generically-named wrappers of mshv_bindings for Unix-based platforms 20 /// 21 pub use { 22 mshv_bindings::hv_cpuid_entry, mshv_bindings::mshv_user_mem_region as MemoryRegion, 23 mshv_bindings::msr_entry, mshv_bindings::AllVpStateComponents, mshv_bindings::CpuId, 24 mshv_bindings::DebugRegisters, mshv_bindings::FloatingPointUnit, 25 mshv_bindings::LapicState as MshvLapicState, mshv_bindings::MiscRegs as MiscRegisters, 26 mshv_bindings::MsrList, mshv_bindings::Msrs as MsrEntries, mshv_bindings::Msrs, 27 mshv_bindings::SegmentRegister as MshvSegmentRegister, 28 mshv_bindings::SpecialRegisters as MshvSpecialRegisters, 29 mshv_bindings::StandardRegisters as MshvStandardRegisters, mshv_bindings::SuspendRegisters, 30 mshv_bindings::TableRegister, mshv_bindings::VcpuEvents, mshv_bindings::XSave as Xsave, 31 mshv_bindings::Xcrs as ExtendedControlRegisters, 32 }; 33 34 #[derive(Clone, Serialize, Deserialize)] 35 pub struct VcpuMshvState { 36 pub msrs: Vec<MsrEntry>, 37 pub vcpu_events: VcpuEvents, 38 pub regs: MshvStandardRegisters, 39 pub sregs: MshvSpecialRegisters, 40 pub fpu: FpuState, 41 pub xcrs: ExtendedControlRegisters, 42 pub dbg: DebugRegisters, 43 pub misc: MiscRegisters, 44 pub vp_states: AllVpStateComponents, 45 } 46 47 #[derive(Clone, Copy, Debug, Default, Serialize, Deserialize)] 48 pub struct MshvClockData { 49 pub ref_time: u64, 50 } 51 52 impl fmt::Display for VcpuMshvState { 53 fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { 54 let expected_num_msrs = self.msrs.len(); 55 let mut msr_entries = vec![vec![0; 2]; expected_num_msrs]; 56 57 for (i, entry) in self.msrs.iter().enumerate() { 58 msr_entries[i][1] = entry.data; 59 msr_entries[i][0] = entry.index as u64; 60 } 61 write!(f, "Number of MSRs: {}: MSRs: {:#010X?}, -- VCPU Events: {:?} -- Standard registers: {:?} Special Registers: {:?} ---- Floating Point Unit: {:?} --- Extended Control Register: {:?} --- DBG: {:?} --- VP States: {:?}", 62 msr_entries.len(), 63 msr_entries, 64 self.vcpu_events, 65 self.regs, 66 self.sregs, 67 self.fpu, 68 self.xcrs, 69 self.dbg, 70 self.vp_states, 71 ) 72 } 73 } 74 75 impl From<SegmentRegister> for MshvSegmentRegister { 76 fn from(s: SegmentRegister) -> Self { 77 Self { 78 base: s.base, 79 limit: s.limit, 80 selector: s.selector, 81 type_: s.type_, 82 present: s.present, 83 dpl: s.dpl, 84 db: s.db, 85 s: s.s, 86 l: s.l, 87 g: s.g, 88 avl: s.avl, 89 unusable: s.unusable, 90 ..Default::default() 91 } 92 } 93 } 94 95 impl From<MshvSegmentRegister> for SegmentRegister { 96 fn from(s: MshvSegmentRegister) -> Self { 97 Self { 98 base: s.base, 99 limit: s.limit, 100 selector: s.selector, 101 type_: s.type_, 102 present: s.present, 103 dpl: s.dpl, 104 db: s.db, 105 s: s.s, 106 l: s.l, 107 g: s.g, 108 avl: s.avl, 109 unusable: s.unusable, 110 } 111 } 112 } 113 114 impl From<DescriptorTable> for TableRegister { 115 fn from(dt: DescriptorTable) -> Self { 116 Self { 117 base: dt.base, 118 limit: dt.limit, 119 } 120 } 121 } 122 123 impl From<TableRegister> for DescriptorTable { 124 fn from(dt: TableRegister) -> Self { 125 Self { 126 base: dt.base, 127 limit: dt.limit, 128 } 129 } 130 } 131 132 impl From<SpecialRegisters> for MshvSpecialRegisters { 133 fn from(s: SpecialRegisters) -> Self { 134 Self { 135 cs: s.cs.into(), 136 ds: s.ds.into(), 137 es: s.es.into(), 138 fs: s.fs.into(), 139 gs: s.gs.into(), 140 ss: s.ss.into(), 141 tr: s.tr.into(), 142 ldt: s.ldt.into(), 143 gdt: s.gdt.into(), 144 idt: s.idt.into(), 145 cr0: s.cr0, 146 cr2: s.cr2, 147 cr3: s.cr3, 148 cr4: s.cr4, 149 cr8: s.cr8, 150 efer: s.efer, 151 apic_base: s.apic_base, 152 interrupt_bitmap: s.interrupt_bitmap, 153 } 154 } 155 } 156 157 impl From<MshvSpecialRegisters> for SpecialRegisters { 158 fn from(s: MshvSpecialRegisters) -> Self { 159 Self { 160 cs: s.cs.into(), 161 ds: s.ds.into(), 162 es: s.es.into(), 163 fs: s.fs.into(), 164 gs: s.gs.into(), 165 ss: s.ss.into(), 166 tr: s.tr.into(), 167 ldt: s.ldt.into(), 168 gdt: s.gdt.into(), 169 idt: s.idt.into(), 170 cr0: s.cr0, 171 cr2: s.cr2, 172 cr3: s.cr3, 173 cr4: s.cr4, 174 cr8: s.cr8, 175 efer: s.efer, 176 apic_base: s.apic_base, 177 interrupt_bitmap: s.interrupt_bitmap, 178 } 179 } 180 } 181 182 impl From<CpuIdEntry> for hv_cpuid_entry { 183 fn from(e: CpuIdEntry) -> Self { 184 Self { 185 function: e.function, 186 index: e.index, 187 flags: e.flags, 188 eax: e.eax, 189 ebx: e.ebx, 190 ecx: e.ecx, 191 edx: e.edx, 192 ..Default::default() 193 } 194 } 195 } 196 197 impl From<hv_cpuid_entry> for CpuIdEntry { 198 fn from(e: hv_cpuid_entry) -> Self { 199 Self { 200 function: e.function, 201 index: e.index, 202 flags: e.flags, 203 eax: e.eax, 204 ebx: e.ebx, 205 ecx: e.ecx, 206 edx: e.edx, 207 } 208 } 209 } 210 211 impl From<FloatingPointUnit> for FpuState { 212 fn from(s: FloatingPointUnit) -> Self { 213 Self { 214 fpr: s.fpr, 215 fcw: s.fcw, 216 fsw: s.fsw, 217 ftwx: s.ftwx, 218 last_opcode: s.last_opcode, 219 last_ip: s.last_ip, 220 last_dp: s.last_dp, 221 xmm: s.xmm, 222 mxcsr: s.mxcsr, 223 } 224 } 225 } 226 227 impl From<FpuState> for FloatingPointUnit { 228 fn from(s: FpuState) -> Self { 229 Self { 230 fpr: s.fpr, 231 fcw: s.fcw, 232 fsw: s.fsw, 233 ftwx: s.ftwx, 234 last_opcode: s.last_opcode, 235 last_ip: s.last_ip, 236 last_dp: s.last_dp, 237 xmm: s.xmm, 238 mxcsr: s.mxcsr, 239 ..Default::default() 240 } 241 } 242 } 243 244 impl From<LapicState> for MshvLapicState { 245 fn from(s: LapicState) -> Self { 246 Self { regs: s.regs } 247 } 248 } 249 250 impl From<MshvLapicState> for LapicState { 251 fn from(s: MshvLapicState) -> Self { 252 Self { regs: s.regs } 253 } 254 } 255 256 impl From<msr_entry> for MsrEntry { 257 fn from(e: msr_entry) -> Self { 258 Self { 259 index: e.index, 260 data: e.data, 261 } 262 } 263 } 264 265 impl From<MsrEntry> for msr_entry { 266 fn from(e: MsrEntry) -> Self { 267 Self { 268 index: e.index, 269 data: e.data, 270 ..Default::default() 271 } 272 } 273 } 274