1 // SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause 2 // 3 // Copyright © 2020, Microsoft Corporation 4 // 5 6 use crate::arch::emulator::PlatformEmulator; 7 #[cfg(target_arch = "x86_64")] 8 use crate::arch::x86::emulator::Emulator; 9 use crate::cpu; 10 use crate::hypervisor; 11 use crate::mshv::emulator::MshvEmulatorContext; 12 use crate::vec_with_array_field; 13 use crate::vm::{self, InterruptSourceConfig, VmOps}; 14 use crate::HypervisorType; 15 use mshv_bindings::*; 16 use mshv_ioctls::{set_registers_64, InterruptRequest, Mshv, NoDatamatch, VcpuFd, VmFd, VmType}; 17 use std::any::Any; 18 use std::collections::HashMap; 19 use std::sync::{Arc, RwLock}; 20 use vfio_ioctls::VfioDeviceFd; 21 use vm::DataMatch; 22 #[cfg(feature = "sev_snp")] 23 mod snp_constants; 24 // x86_64 dependencies 25 #[cfg(target_arch = "x86_64")] 26 pub mod x86_64; 27 #[cfg(target_arch = "x86_64")] 28 use crate::arch::x86::{CpuIdEntry, FpuState, MsrEntry}; 29 #[cfg(target_arch = "x86_64")] 30 use crate::ClockData; 31 use crate::{ 32 CpuState, IoEventAddress, IrqRoutingEntry, MpState, UserMemoryRegion, 33 USER_MEMORY_REGION_ADJUSTABLE, USER_MEMORY_REGION_EXECUTE, USER_MEMORY_REGION_READ, 34 USER_MEMORY_REGION_WRITE, 35 }; 36 #[cfg(feature = "sev_snp")] 37 use igvm_defs::IGVM_VHS_SNP_ID_BLOCK; 38 #[cfg(feature = "sev_snp")] 39 use snp_constants::*; 40 #[cfg(target_arch = "x86_64")] 41 use std::fs::File; 42 use std::os::unix::io::AsRawFd; 43 use vmm_sys_util::eventfd::EventFd; 44 #[cfg(target_arch = "x86_64")] 45 pub use x86_64::*; 46 #[cfg(target_arch = "x86_64")] 47 pub use x86_64::{emulator, VcpuMshvState}; 48 49 const DIRTY_BITMAP_CLEAR_DIRTY: u64 = 0x4; 50 const DIRTY_BITMAP_SET_DIRTY: u64 = 0x8; 51 52 /// 53 /// Export generically-named wrappers of mshv-bindings for Unix-based platforms 54 /// 55 pub use { 56 mshv_bindings::mshv_create_device as CreateDevice, 57 mshv_bindings::mshv_device_attr as DeviceAttr, mshv_ioctls::DeviceFd, 58 }; 59 60 pub const PAGE_SHIFT: usize = 12; 61 62 impl From<mshv_user_mem_region> for UserMemoryRegion { 63 fn from(region: mshv_user_mem_region) -> Self { 64 let mut flags: u32 = 0; 65 if region.flags & HV_MAP_GPA_READABLE != 0 { 66 flags |= USER_MEMORY_REGION_READ; 67 } 68 if region.flags & HV_MAP_GPA_WRITABLE != 0 { 69 flags |= USER_MEMORY_REGION_WRITE; 70 } 71 if region.flags & HV_MAP_GPA_EXECUTABLE != 0 { 72 flags |= USER_MEMORY_REGION_EXECUTE; 73 } 74 if region.flags & HV_MAP_GPA_ADJUSTABLE != 0 { 75 flags |= USER_MEMORY_REGION_ADJUSTABLE; 76 } 77 78 UserMemoryRegion { 79 guest_phys_addr: (region.guest_pfn << PAGE_SHIFT as u64) 80 + (region.userspace_addr & ((1 << PAGE_SHIFT) - 1)), 81 memory_size: region.size, 82 userspace_addr: region.userspace_addr, 83 flags, 84 ..Default::default() 85 } 86 } 87 } 88 89 #[cfg(target_arch = "x86_64")] 90 impl From<MshvClockData> for ClockData { 91 fn from(d: MshvClockData) -> Self { 92 ClockData::Mshv(d) 93 } 94 } 95 96 #[cfg(target_arch = "x86_64")] 97 impl From<ClockData> for MshvClockData { 98 fn from(ms: ClockData) -> Self { 99 match ms { 100 ClockData::Mshv(s) => s, 101 /* Needed in case other hypervisors are enabled */ 102 #[allow(unreachable_patterns)] 103 _ => unreachable!("MSHV clock data is not valid"), 104 } 105 } 106 } 107 108 impl From<UserMemoryRegion> for mshv_user_mem_region { 109 fn from(region: UserMemoryRegion) -> Self { 110 let mut flags: u32 = 0; 111 if region.flags & USER_MEMORY_REGION_READ != 0 { 112 flags |= HV_MAP_GPA_READABLE; 113 } 114 if region.flags & USER_MEMORY_REGION_WRITE != 0 { 115 flags |= HV_MAP_GPA_WRITABLE; 116 } 117 if region.flags & USER_MEMORY_REGION_EXECUTE != 0 { 118 flags |= HV_MAP_GPA_EXECUTABLE; 119 } 120 if region.flags & USER_MEMORY_REGION_ADJUSTABLE != 0 { 121 flags |= HV_MAP_GPA_ADJUSTABLE; 122 } 123 124 mshv_user_mem_region { 125 guest_pfn: region.guest_phys_addr >> PAGE_SHIFT, 126 size: region.memory_size, 127 userspace_addr: region.userspace_addr, 128 flags, 129 } 130 } 131 } 132 133 impl From<mshv_ioctls::IoEventAddress> for IoEventAddress { 134 fn from(a: mshv_ioctls::IoEventAddress) -> Self { 135 match a { 136 mshv_ioctls::IoEventAddress::Pio(x) => Self::Pio(x), 137 mshv_ioctls::IoEventAddress::Mmio(x) => Self::Mmio(x), 138 } 139 } 140 } 141 142 impl From<IoEventAddress> for mshv_ioctls::IoEventAddress { 143 fn from(a: IoEventAddress) -> Self { 144 match a { 145 IoEventAddress::Pio(x) => Self::Pio(x), 146 IoEventAddress::Mmio(x) => Self::Mmio(x), 147 } 148 } 149 } 150 151 impl From<VcpuMshvState> for CpuState { 152 fn from(s: VcpuMshvState) -> Self { 153 CpuState::Mshv(s) 154 } 155 } 156 157 impl From<CpuState> for VcpuMshvState { 158 fn from(s: CpuState) -> Self { 159 match s { 160 CpuState::Mshv(s) => s, 161 /* Needed in case other hypervisors are enabled */ 162 #[allow(unreachable_patterns)] 163 _ => panic!("CpuState is not valid"), 164 } 165 } 166 } 167 168 impl From<mshv_msi_routing_entry> for IrqRoutingEntry { 169 fn from(s: mshv_msi_routing_entry) -> Self { 170 IrqRoutingEntry::Mshv(s) 171 } 172 } 173 174 impl From<IrqRoutingEntry> for mshv_msi_routing_entry { 175 fn from(e: IrqRoutingEntry) -> Self { 176 match e { 177 IrqRoutingEntry::Mshv(e) => e, 178 /* Needed in case other hypervisors are enabled */ 179 #[allow(unreachable_patterns)] 180 _ => panic!("IrqRoutingEntry is not valid"), 181 } 182 } 183 } 184 185 struct MshvDirtyLogSlot { 186 guest_pfn: u64, 187 memory_size: u64, 188 } 189 190 /// Wrapper over mshv system ioctls. 191 pub struct MshvHypervisor { 192 mshv: Mshv, 193 } 194 195 impl MshvHypervisor { 196 #[cfg(target_arch = "x86_64")] 197 /// 198 /// Retrieve the list of MSRs supported by MSHV. 199 /// 200 fn get_msr_list(&self) -> hypervisor::Result<MsrList> { 201 self.mshv 202 .get_msr_index_list() 203 .map_err(|e| hypervisor::HypervisorError::GetMsrList(e.into())) 204 } 205 } 206 207 impl MshvHypervisor { 208 /// Create a hypervisor based on Mshv 209 #[allow(clippy::new_ret_no_self)] 210 pub fn new() -> hypervisor::Result<Arc<dyn hypervisor::Hypervisor>> { 211 let mshv_obj = 212 Mshv::new().map_err(|e| hypervisor::HypervisorError::HypervisorCreate(e.into()))?; 213 Ok(Arc::new(MshvHypervisor { mshv: mshv_obj })) 214 } 215 /// Check if the hypervisor is available 216 pub fn is_available() -> hypervisor::Result<bool> { 217 match std::fs::metadata("/dev/mshv") { 218 Ok(_) => Ok(true), 219 Err(err) if err.kind() == std::io::ErrorKind::NotFound => Ok(false), 220 Err(err) => Err(hypervisor::HypervisorError::HypervisorAvailableCheck( 221 err.into(), 222 )), 223 } 224 } 225 } 226 227 /// Implementation of Hypervisor trait for Mshv 228 /// 229 /// # Examples 230 /// 231 /// ``` 232 /// # use hypervisor::mshv::MshvHypervisor; 233 /// # use std::sync::Arc; 234 /// let mshv = MshvHypervisor::new().unwrap(); 235 /// let hypervisor = Arc::new(mshv); 236 /// let vm = hypervisor.create_vm().expect("new VM fd creation failed"); 237 /// ``` 238 impl hypervisor::Hypervisor for MshvHypervisor { 239 /// 240 /// Returns the type of the hypervisor 241 /// 242 fn hypervisor_type(&self) -> HypervisorType { 243 HypervisorType::Mshv 244 } 245 246 fn create_vm_with_type(&self, vm_type: u64) -> hypervisor::Result<Arc<dyn crate::Vm>> { 247 let mshv_vm_type: VmType = match VmType::try_from(vm_type) { 248 Ok(vm_type) => vm_type, 249 Err(_) => return Err(hypervisor::HypervisorError::UnsupportedVmType()), 250 }; 251 let fd: VmFd; 252 loop { 253 match self.mshv.create_vm_with_type(mshv_vm_type) { 254 Ok(res) => fd = res, 255 Err(e) => { 256 if e.errno() == libc::EINTR { 257 // If the error returned is EINTR, which means the 258 // ioctl has been interrupted, we have to retry as 259 // this can't be considered as a regular error. 260 continue; 261 } else { 262 return Err(hypervisor::HypervisorError::VmCreate(e.into())); 263 } 264 } 265 } 266 break; 267 } 268 269 // Set additional partition property for SEV-SNP partition. 270 #[cfg(target_arch = "x86_64")] 271 if mshv_vm_type == VmType::Snp { 272 let snp_policy = snp::get_default_snp_guest_policy(); 273 let vmgexit_offloads = snp::get_default_vmgexit_offload_features(); 274 // SAFETY: access union fields 275 unsafe { 276 debug!( 277 "Setting the partition isolation policy as: 0x{:x}", 278 snp_policy.as_uint64 279 ); 280 fd.set_partition_property( 281 hv_partition_property_code_HV_PARTITION_PROPERTY_ISOLATION_POLICY, 282 snp_policy.as_uint64, 283 ) 284 .map_err(|e| hypervisor::HypervisorError::SetPartitionProperty(e.into()))?; 285 debug!( 286 "Setting the partition property to enable VMGEXIT offloads as : 0x{:x}", 287 vmgexit_offloads.as_uint64 288 ); 289 fd.set_partition_property( 290 hv_partition_property_code_HV_PARTITION_PROPERTY_SEV_VMGEXIT_OFFLOADS, 291 vmgexit_offloads.as_uint64, 292 ) 293 .map_err(|e| hypervisor::HypervisorError::SetPartitionProperty(e.into()))?; 294 } 295 } 296 297 // Default Microsoft Hypervisor behavior for unimplemented MSR is to 298 // send a fault to the guest if it tries to access it. It is possible 299 // to override this behavior with a more suitable option i.e., ignore 300 // writes from the guest and return zero in attempt to read unimplemented 301 // MSR. 302 #[cfg(target_arch = "x86_64")] 303 fd.set_partition_property( 304 hv_partition_property_code_HV_PARTITION_PROPERTY_UNIMPLEMENTED_MSR_ACTION, 305 hv_unimplemented_msr_action_HV_UNIMPLEMENTED_MSR_ACTION_IGNORE_WRITE_READ_ZERO as u64, 306 ) 307 .map_err(|e| hypervisor::HypervisorError::SetPartitionProperty(e.into()))?; 308 309 // Always create a frozen partition 310 fd.set_partition_property( 311 hv_partition_property_code_HV_PARTITION_PROPERTY_TIME_FREEZE, 312 1u64, 313 ) 314 .map_err(|e| hypervisor::HypervisorError::SetPartitionProperty(e.into()))?; 315 316 let vm_fd = Arc::new(fd); 317 318 #[cfg(target_arch = "x86_64")] 319 { 320 let msr_list = self.get_msr_list()?; 321 let num_msrs = msr_list.as_fam_struct_ref().nmsrs as usize; 322 let mut msrs: Vec<MsrEntry> = vec![ 323 MsrEntry { 324 ..Default::default() 325 }; 326 num_msrs 327 ]; 328 let indices = msr_list.as_slice(); 329 for (pos, index) in indices.iter().enumerate() { 330 msrs[pos].index = *index; 331 } 332 333 Ok(Arc::new(MshvVm { 334 fd: vm_fd, 335 msrs, 336 dirty_log_slots: Arc::new(RwLock::new(HashMap::new())), 337 #[cfg(feature = "sev_snp")] 338 sev_snp_enabled: mshv_vm_type == VmType::Snp, 339 })) 340 } 341 342 #[cfg(target_arch = "aarch64")] 343 { 344 Ok(Arc::new(MshvVm { 345 fd: vm_fd, 346 dirty_log_slots: Arc::new(RwLock::new(HashMap::new())), 347 })) 348 } 349 } 350 351 /// Create a mshv vm object and return the object as Vm trait object 352 /// 353 /// # Examples 354 /// 355 /// ``` 356 /// # extern crate hypervisor; 357 /// # use hypervisor::mshv::MshvHypervisor; 358 /// use hypervisor::mshv::MshvVm; 359 /// let hypervisor = MshvHypervisor::new().unwrap(); 360 /// let vm = hypervisor.create_vm().unwrap(); 361 /// ``` 362 fn create_vm(&self) -> hypervisor::Result<Arc<dyn vm::Vm>> { 363 let vm_type = 0; 364 self.create_vm_with_type(vm_type) 365 } 366 #[cfg(target_arch = "x86_64")] 367 /// 368 /// Get the supported CpuID 369 /// 370 fn get_supported_cpuid(&self) -> hypervisor::Result<Vec<CpuIdEntry>> { 371 let mut cpuid = Vec::new(); 372 let functions: [u32; 2] = [0x1, 0xb]; 373 374 for function in functions { 375 cpuid.push(CpuIdEntry { 376 function, 377 ..Default::default() 378 }); 379 } 380 Ok(cpuid) 381 } 382 383 /// Get maximum number of vCPUs 384 fn get_max_vcpus(&self) -> u32 { 385 // TODO: Using HV_MAXIMUM_PROCESSORS would be better 386 // but the ioctl API is limited to u8 387 256 388 } 389 } 390 391 /// Vcpu struct for Microsoft Hypervisor 392 pub struct MshvVcpu { 393 fd: VcpuFd, 394 vp_index: u8, 395 #[cfg(target_arch = "x86_64")] 396 cpuid: Vec<CpuIdEntry>, 397 #[cfg(target_arch = "x86_64")] 398 msrs: Vec<MsrEntry>, 399 vm_ops: Option<Arc<dyn vm::VmOps>>, 400 vm_fd: Arc<VmFd>, 401 } 402 403 /// Implementation of Vcpu trait for Microsoft Hypervisor 404 /// 405 /// # Examples 406 /// 407 /// ``` 408 /// # use hypervisor::mshv::MshvHypervisor; 409 /// # use std::sync::Arc; 410 /// let mshv = MshvHypervisor::new().unwrap(); 411 /// let hypervisor = Arc::new(mshv); 412 /// let vm = hypervisor.create_vm().expect("new VM fd creation failed"); 413 /// let vcpu = vm.create_vcpu(0, None).unwrap(); 414 /// ``` 415 impl cpu::Vcpu for MshvVcpu { 416 #[cfg(target_arch = "x86_64")] 417 /// 418 /// Returns the vCPU general purpose registers. 419 /// 420 fn get_regs(&self) -> cpu::Result<crate::arch::x86::StandardRegisters> { 421 Ok(self 422 .fd 423 .get_regs() 424 .map_err(|e| cpu::HypervisorCpuError::GetStandardRegs(e.into()))? 425 .into()) 426 } 427 428 #[cfg(target_arch = "x86_64")] 429 /// 430 /// Sets the vCPU general purpose registers. 431 /// 432 fn set_regs(&self, regs: &crate::arch::x86::StandardRegisters) -> cpu::Result<()> { 433 let regs = (*regs).into(); 434 self.fd 435 .set_regs(®s) 436 .map_err(|e| cpu::HypervisorCpuError::SetStandardRegs(e.into())) 437 } 438 439 #[cfg(target_arch = "x86_64")] 440 /// 441 /// Returns the vCPU special registers. 442 /// 443 fn get_sregs(&self) -> cpu::Result<crate::arch::x86::SpecialRegisters> { 444 Ok(self 445 .fd 446 .get_sregs() 447 .map_err(|e| cpu::HypervisorCpuError::GetSpecialRegs(e.into()))? 448 .into()) 449 } 450 451 #[cfg(target_arch = "x86_64")] 452 /// 453 /// Sets the vCPU special registers. 454 /// 455 fn set_sregs(&self, sregs: &crate::arch::x86::SpecialRegisters) -> cpu::Result<()> { 456 let sregs = (*sregs).into(); 457 self.fd 458 .set_sregs(&sregs) 459 .map_err(|e| cpu::HypervisorCpuError::SetSpecialRegs(e.into())) 460 } 461 462 #[cfg(target_arch = "x86_64")] 463 /// 464 /// Returns the floating point state (FPU) from the vCPU. 465 /// 466 fn get_fpu(&self) -> cpu::Result<FpuState> { 467 Ok(self 468 .fd 469 .get_fpu() 470 .map_err(|e| cpu::HypervisorCpuError::GetFloatingPointRegs(e.into()))? 471 .into()) 472 } 473 474 #[cfg(target_arch = "x86_64")] 475 /// 476 /// Set the floating point state (FPU) of a vCPU. 477 /// 478 fn set_fpu(&self, fpu: &FpuState) -> cpu::Result<()> { 479 let fpu: mshv_bindings::FloatingPointUnit = (*fpu).clone().into(); 480 self.fd 481 .set_fpu(&fpu) 482 .map_err(|e| cpu::HypervisorCpuError::SetFloatingPointRegs(e.into())) 483 } 484 485 #[cfg(target_arch = "x86_64")] 486 /// 487 /// Returns the model-specific registers (MSR) for this vCPU. 488 /// 489 fn get_msrs(&self, msrs: &mut Vec<MsrEntry>) -> cpu::Result<usize> { 490 let mshv_msrs: Vec<msr_entry> = msrs.iter().map(|e| (*e).into()).collect(); 491 let mut mshv_msrs = MsrEntries::from_entries(&mshv_msrs).unwrap(); 492 let succ = self 493 .fd 494 .get_msrs(&mut mshv_msrs) 495 .map_err(|e| cpu::HypervisorCpuError::GetMsrEntries(e.into()))?; 496 497 msrs[..succ].copy_from_slice( 498 &mshv_msrs.as_slice()[..succ] 499 .iter() 500 .map(|e| (*e).into()) 501 .collect::<Vec<MsrEntry>>(), 502 ); 503 504 Ok(succ) 505 } 506 507 #[cfg(target_arch = "x86_64")] 508 /// 509 /// Setup the model-specific registers (MSR) for this vCPU. 510 /// Returns the number of MSR entries actually written. 511 /// 512 fn set_msrs(&self, msrs: &[MsrEntry]) -> cpu::Result<usize> { 513 let mshv_msrs: Vec<msr_entry> = msrs.iter().map(|e| (*e).into()).collect(); 514 let mshv_msrs = MsrEntries::from_entries(&mshv_msrs).unwrap(); 515 self.fd 516 .set_msrs(&mshv_msrs) 517 .map_err(|e| cpu::HypervisorCpuError::SetMsrEntries(e.into())) 518 } 519 520 #[cfg(target_arch = "x86_64")] 521 /// 522 /// X86 specific call to enable HyperV SynIC 523 /// 524 fn enable_hyperv_synic(&self) -> cpu::Result<()> { 525 /* We always have SynIC enabled on MSHV */ 526 Ok(()) 527 } 528 529 #[allow(non_upper_case_globals)] 530 fn run(&self) -> std::result::Result<cpu::VmExit, cpu::HypervisorCpuError> { 531 let hv_message: hv_message = hv_message::default(); 532 match self.fd.run(hv_message) { 533 Ok(x) => match x.header.message_type { 534 hv_message_type_HVMSG_X64_HALT => { 535 debug!("HALT"); 536 Ok(cpu::VmExit::Reset) 537 } 538 hv_message_type_HVMSG_UNRECOVERABLE_EXCEPTION => { 539 warn!("TRIPLE FAULT"); 540 Ok(cpu::VmExit::Shutdown) 541 } 542 #[cfg(target_arch = "x86_64")] 543 hv_message_type_HVMSG_X64_IO_PORT_INTERCEPT => { 544 let info = x.to_ioport_info().unwrap(); 545 let access_info = info.access_info; 546 // SAFETY: access_info is valid, otherwise we won't be here 547 let len = unsafe { access_info.__bindgen_anon_1.access_size() } as usize; 548 let is_write = info.header.intercept_access_type == 1; 549 let port = info.port_number; 550 let mut data: [u8; 4] = [0; 4]; 551 let mut ret_rax = info.rax; 552 553 /* 554 * XXX: Ignore QEMU fw_cfg (0x5xx) and debug console (0x402) ports. 555 * 556 * Cloud Hypervisor doesn't support fw_cfg at the moment. It does support 0x402 557 * under the "fwdebug" feature flag. But that feature is not enabled by default 558 * and is considered legacy. 559 * 560 * OVMF unconditionally pokes these IO ports with string IO. 561 * 562 * Instead of trying to implement string IO support now which does not do much 563 * now, skip those ports explicitly to avoid panicking. 564 * 565 * Proper string IO support can be added once we gain the ability to translate 566 * guest virtual addresses to guest physical addresses on MSHV. 567 */ 568 match port { 569 0x402 | 0x510 | 0x511 | 0x514 => { 570 let insn_len = info.header.instruction_length() as u64; 571 572 /* Advance RIP and update RAX */ 573 let arr_reg_name_value = [ 574 ( 575 hv_register_name_HV_X64_REGISTER_RIP, 576 info.header.rip + insn_len, 577 ), 578 (hv_register_name_HV_X64_REGISTER_RAX, ret_rax), 579 ]; 580 set_registers_64!(self.fd, arr_reg_name_value) 581 .map_err(|e| cpu::HypervisorCpuError::SetRegister(e.into()))?; 582 return Ok(cpu::VmExit::Ignore); 583 } 584 _ => {} 585 } 586 587 assert!( 588 // SAFETY: access_info is valid, otherwise we won't be here 589 (unsafe { access_info.__bindgen_anon_1.string_op() } != 1), 590 "String IN/OUT not supported" 591 ); 592 assert!( 593 // SAFETY: access_info is valid, otherwise we won't be here 594 (unsafe { access_info.__bindgen_anon_1.rep_prefix() } != 1), 595 "Rep IN/OUT not supported" 596 ); 597 598 if is_write { 599 let data = (info.rax as u32).to_le_bytes(); 600 if let Some(vm_ops) = &self.vm_ops { 601 vm_ops 602 .pio_write(port.into(), &data[0..len]) 603 .map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()))?; 604 } 605 } else { 606 if let Some(vm_ops) = &self.vm_ops { 607 vm_ops 608 .pio_read(port.into(), &mut data[0..len]) 609 .map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()))?; 610 } 611 612 let v = u32::from_le_bytes(data); 613 /* Preserve high bits in EAX but clear out high bits in RAX */ 614 let mask = 0xffffffff >> (32 - len * 8); 615 let eax = (info.rax as u32 & !mask) | (v & mask); 616 ret_rax = eax as u64; 617 } 618 619 let insn_len = info.header.instruction_length() as u64; 620 621 /* Advance RIP and update RAX */ 622 let arr_reg_name_value = [ 623 ( 624 hv_register_name_HV_X64_REGISTER_RIP, 625 info.header.rip + insn_len, 626 ), 627 (hv_register_name_HV_X64_REGISTER_RAX, ret_rax), 628 ]; 629 set_registers_64!(self.fd, arr_reg_name_value) 630 .map_err(|e| cpu::HypervisorCpuError::SetRegister(e.into()))?; 631 Ok(cpu::VmExit::Ignore) 632 } 633 #[cfg(target_arch = "x86_64")] 634 msg_type @ (hv_message_type_HVMSG_UNMAPPED_GPA 635 | hv_message_type_HVMSG_GPA_INTERCEPT) => { 636 let info = x.to_memory_info().unwrap(); 637 let insn_len = info.instruction_byte_count as usize; 638 let gva = info.guest_virtual_address; 639 let gpa = info.guest_physical_address; 640 641 debug!("Exit ({:?}) GVA {:x} GPA {:x}", msg_type, gva, gpa); 642 643 let mut context = MshvEmulatorContext { 644 vcpu: self, 645 map: (gva, gpa), 646 }; 647 648 // Create a new emulator. 649 let mut emul = Emulator::new(&mut context); 650 651 // Emulate the trapped instruction, and only the first one. 652 let new_state = emul 653 .emulate_first_insn( 654 self.vp_index as usize, 655 &info.instruction_bytes[..insn_len], 656 ) 657 .map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()))?; 658 659 // Set CPU state back. 660 context 661 .set_cpu_state(self.vp_index as usize, new_state) 662 .map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()))?; 663 664 Ok(cpu::VmExit::Ignore) 665 } 666 #[cfg(feature = "sev_snp")] 667 hv_message_type_HVMSG_GPA_ATTRIBUTE_INTERCEPT => { 668 let info = x.to_gpa_attribute_info().unwrap(); 669 let host_vis = info.__bindgen_anon_1.host_visibility(); 670 if host_vis >= HV_MAP_GPA_READABLE | HV_MAP_GPA_WRITABLE { 671 warn!("Ignored attribute intercept with full host visibility"); 672 return Ok(cpu::VmExit::Ignore); 673 } 674 675 let num_ranges = info.__bindgen_anon_1.range_count(); 676 assert!(num_ranges >= 1); 677 if num_ranges > 1 { 678 return Err(cpu::HypervisorCpuError::RunVcpu(anyhow!( 679 "Unhandled VCPU exit(GPA_ATTRIBUTE_INTERCEPT): Expected num_ranges to be 1 but found num_ranges {:?}", 680 num_ranges 681 ))); 682 } 683 684 // TODO: we could also deny the request with HvCallCompleteIntercept 685 let mut gpas = Vec::new(); 686 let ranges = info.ranges; 687 let (gfn_start, gfn_count) = snp::parse_gpa_range(ranges[0]).unwrap(); 688 debug!( 689 "Releasing pages: gfn_start: {:x?}, gfn_count: {:?}", 690 gfn_start, gfn_count 691 ); 692 let gpa_start = gfn_start * HV_PAGE_SIZE as u64; 693 for i in 0..gfn_count { 694 gpas.push(gpa_start + i * HV_PAGE_SIZE as u64); 695 } 696 697 let mut gpa_list = 698 vec_with_array_field::<mshv_modify_gpa_host_access, u64>(gpas.len()); 699 gpa_list[0].gpa_list_size = gpas.len() as u64; 700 gpa_list[0].host_access = host_vis; 701 gpa_list[0].acquire = 0; 702 gpa_list[0].flags = 0; 703 704 // SAFETY: gpa_list initialized with gpas.len() and now it is being turned into 705 // gpas_slice with gpas.len() again. It is guaranteed to be large enough to hold 706 // everything from gpas. 707 unsafe { 708 let gpas_slice: &mut [u64] = gpa_list[0].gpa_list.as_mut_slice(gpas.len()); 709 gpas_slice.copy_from_slice(gpas.as_slice()); 710 } 711 712 self.vm_fd 713 .modify_gpa_host_access(&gpa_list[0]) 714 .map_err(|e| cpu::HypervisorCpuError::RunVcpu(anyhow!( 715 "Unhandled VCPU exit: attribute intercept - couldn't modify host access {}", e 716 )))?; 717 Ok(cpu::VmExit::Ignore) 718 } 719 #[cfg(target_arch = "x86_64")] 720 hv_message_type_HVMSG_UNACCEPTED_GPA => { 721 let info = x.to_memory_info().unwrap(); 722 let gva = info.guest_virtual_address; 723 let gpa = info.guest_physical_address; 724 725 Err(cpu::HypervisorCpuError::RunVcpu(anyhow!( 726 "Unhandled VCPU exit: Unaccepted GPA({:x}) found at GVA({:x})", 727 gpa, 728 gva, 729 ))) 730 } 731 #[cfg(target_arch = "x86_64")] 732 hv_message_type_HVMSG_X64_CPUID_INTERCEPT => { 733 let info = x.to_cpuid_info().unwrap(); 734 debug!("cpuid eax: {:x}", { info.rax }); 735 Ok(cpu::VmExit::Ignore) 736 } 737 #[cfg(target_arch = "x86_64")] 738 hv_message_type_HVMSG_X64_MSR_INTERCEPT => { 739 let info = x.to_msr_info().unwrap(); 740 if info.header.intercept_access_type == 0 { 741 debug!("msr read: {:x}", { info.msr_number }); 742 } else { 743 debug!("msr write: {:x}", { info.msr_number }); 744 } 745 Ok(cpu::VmExit::Ignore) 746 } 747 #[cfg(target_arch = "x86_64")] 748 hv_message_type_HVMSG_X64_EXCEPTION_INTERCEPT => { 749 //TODO: Handler for VMCALL here. 750 let info = x.to_exception_info().unwrap(); 751 debug!("Exception Info {:?}", { info.exception_vector }); 752 Ok(cpu::VmExit::Ignore) 753 } 754 #[cfg(target_arch = "x86_64")] 755 hv_message_type_HVMSG_X64_APIC_EOI => { 756 let info = x.to_apic_eoi_info().unwrap(); 757 // The kernel should dispatch the EOI to the correct thread. 758 // Check the VP index is the same as the one we have. 759 assert!(info.vp_index == self.vp_index as u32); 760 // The interrupt vector in info is u32, but x86 only supports 256 vectors. 761 // There is no good way to recover from this if the hypervisor messes around. 762 // Just unwrap. 763 Ok(cpu::VmExit::IoapicEoi( 764 info.interrupt_vector.try_into().unwrap(), 765 )) 766 } 767 #[cfg(feature = "sev_snp")] 768 hv_message_type_HVMSG_X64_SEV_VMGEXIT_INTERCEPT => { 769 let info = x.to_vmg_intercept_info().unwrap(); 770 let ghcb_data = info.ghcb_msr >> GHCB_INFO_BIT_WIDTH; 771 let ghcb_msr = svm_ghcb_msr { 772 as_uint64: info.ghcb_msr, 773 }; 774 // SAFETY: Accessing a union element from bindgen generated bindings. 775 let ghcb_op = unsafe { ghcb_msr.__bindgen_anon_2.ghcb_info() as u32 }; 776 // Sanity check on the header fields before handling other operations. 777 assert!(info.header.intercept_access_type == HV_INTERCEPT_ACCESS_EXECUTE as u8); 778 779 match ghcb_op { 780 GHCB_INFO_HYP_FEATURE_REQUEST => { 781 // Pre-condition: GHCB data must be zero 782 assert!(ghcb_data == 0); 783 let mut ghcb_response = GHCB_INFO_HYP_FEATURE_RESPONSE as u64; 784 // Indicate support for basic SEV-SNP features 785 ghcb_response |= 786 (GHCB_HYP_FEATURE_SEV_SNP << GHCB_INFO_BIT_WIDTH) as u64; 787 // Indicate support for SEV-SNP AP creation 788 ghcb_response |= (GHCB_HYP_FEATURE_SEV_SNP_AP_CREATION 789 << GHCB_INFO_BIT_WIDTH) 790 as u64; 791 debug!( 792 "GHCB_INFO_HYP_FEATURE_REQUEST: Supported features: {:0x}", 793 ghcb_response 794 ); 795 let arr_reg_name_value = 796 [(hv_register_name_HV_X64_REGISTER_GHCB, ghcb_response)]; 797 set_registers_64!(self.fd, arr_reg_name_value) 798 .map_err(|e| cpu::HypervisorCpuError::SetRegister(e.into()))?; 799 } 800 GHCB_INFO_REGISTER_REQUEST => { 801 let mut ghcb_gpa = hv_x64_register_sev_ghcb::default(); 802 // SAFETY: Accessing a union element from bindgen generated bindings. 803 unsafe { 804 ghcb_gpa.__bindgen_anon_1.set_enabled(1); 805 ghcb_gpa 806 .__bindgen_anon_1 807 .set_page_number(ghcb_msr.__bindgen_anon_2.gpa_page_number()); 808 } 809 // SAFETY: Accessing a union element from bindgen generated bindings. 810 let reg_name_value = unsafe { 811 [( 812 hv_register_name_HV_X64_REGISTER_SEV_GHCB_GPA, 813 ghcb_gpa.as_uint64, 814 )] 815 }; 816 817 set_registers_64!(self.fd, reg_name_value) 818 .map_err(|e| cpu::HypervisorCpuError::SetRegister(e.into()))?; 819 820 let mut resp_ghcb_msr = svm_ghcb_msr::default(); 821 // SAFETY: Accessing a union element from bindgen generated bindings. 822 unsafe { 823 resp_ghcb_msr 824 .__bindgen_anon_2 825 .set_ghcb_info(GHCB_INFO_REGISTER_RESPONSE as u64); 826 resp_ghcb_msr.__bindgen_anon_2.set_gpa_page_number( 827 ghcb_msr.__bindgen_anon_2.gpa_page_number(), 828 ); 829 } 830 // SAFETY: Accessing a union element from bindgen generated bindings. 831 let reg_name_value = unsafe { 832 [( 833 hv_register_name_HV_X64_REGISTER_GHCB, 834 resp_ghcb_msr.as_uint64, 835 )] 836 }; 837 838 set_registers_64!(self.fd, reg_name_value) 839 .map_err(|e| cpu::HypervisorCpuError::SetRegister(e.into()))?; 840 } 841 GHCB_INFO_SEV_INFO_REQUEST => { 842 let sev_cpuid_function = 0x8000_001F; 843 let cpu_leaf = self 844 .fd 845 .get_cpuid_values(sev_cpuid_function, 0, 0, 0) 846 .unwrap(); 847 let ebx = cpu_leaf[1]; 848 // First 6-byte of EBX represents page table encryption bit number 849 let pbit_encryption = (ebx & 0x3f) as u8; 850 let mut ghcb_response = GHCB_INFO_SEV_INFO_RESPONSE as u64; 851 852 // GHCBData[63:48] specifies the maximum GHCB protocol version supported 853 ghcb_response |= (GHCB_PROTOCOL_VERSION_MAX as u64) << 48; 854 // GHCBData[47:32] specifies the minimum GHCB protocol version supported 855 ghcb_response |= (GHCB_PROTOCOL_VERSION_MIN as u64) << 32; 856 // GHCBData[31:24] specifies the SEV page table encryption bit number. 857 ghcb_response |= (pbit_encryption as u64) << 24; 858 859 let arr_reg_name_value = 860 [(hv_register_name_HV_X64_REGISTER_GHCB, ghcb_response)]; 861 set_registers_64!(self.fd, arr_reg_name_value) 862 .map_err(|e| cpu::HypervisorCpuError::SetRegister(e.into()))?; 863 } 864 GHCB_INFO_NORMAL => { 865 let exit_code = 866 info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_code as u32; 867 // SAFETY: Accessing a union element from bindgen generated bindings. 868 let pfn = unsafe { ghcb_msr.__bindgen_anon_2.gpa_page_number() }; 869 let ghcb_gpa = pfn << GHCB_INFO_BIT_WIDTH; 870 match exit_code { 871 SVM_EXITCODE_HV_DOORBELL_PAGE => { 872 let exit_info1 = 873 info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_info1 as u32; 874 match exit_info1 { 875 SVM_NAE_HV_DOORBELL_PAGE_GET_PREFERRED => { 876 // Hypervisor does not have any preference for doorbell GPA. 877 let preferred_doorbell_gpa: u64 = 0xFFFFFFFFFFFFFFFF; 878 let mut swei2_rw_gpa_arg = 879 mshv_bindings::mshv_read_write_gpa { 880 base_gpa: ghcb_gpa + GHCB_SW_EXITINFO2_OFFSET, 881 byte_count: std::mem::size_of::<u64>() as u32, 882 ..Default::default() 883 }; 884 swei2_rw_gpa_arg.data.copy_from_slice( 885 &preferred_doorbell_gpa.to_le_bytes(), 886 ); 887 self.fd.gpa_write(&mut swei2_rw_gpa_arg).map_err( 888 |e| cpu::HypervisorCpuError::GpaWrite(e.into()), 889 )?; 890 } 891 SVM_NAE_HV_DOORBELL_PAGE_SET => { 892 let exit_info2 = info 893 .__bindgen_anon_2 894 .__bindgen_anon_1 895 .sw_exit_info2; 896 let mut ghcb_doorbell_gpa = 897 hv_x64_register_sev_hv_doorbell::default(); 898 // SAFETY: Accessing a union element from bindgen generated bindings. 899 unsafe { 900 ghcb_doorbell_gpa.__bindgen_anon_1.set_enabled(1); 901 ghcb_doorbell_gpa 902 .__bindgen_anon_1 903 .set_page_number(exit_info2 >> PAGE_SHIFT); 904 } 905 // SAFETY: Accessing a union element from bindgen generated bindings. 906 let reg_names = unsafe { 907 [( 908 hv_register_name_HV_X64_REGISTER_SEV_DOORBELL_GPA, 909 ghcb_doorbell_gpa.as_uint64, 910 )] 911 }; 912 set_registers_64!(self.fd, reg_names).map_err(|e| { 913 cpu::HypervisorCpuError::SetRegister(e.into()) 914 })?; 915 916 let mut swei2_rw_gpa_arg = 917 mshv_bindings::mshv_read_write_gpa { 918 base_gpa: ghcb_gpa + GHCB_SW_EXITINFO2_OFFSET, 919 byte_count: std::mem::size_of::<u64>() as u32, 920 ..Default::default() 921 }; 922 swei2_rw_gpa_arg.data[0..8] 923 .copy_from_slice(&exit_info2.to_le_bytes()); 924 self.fd.gpa_write(&mut swei2_rw_gpa_arg).map_err( 925 |e| cpu::HypervisorCpuError::GpaWrite(e.into()), 926 )?; 927 928 // Clear the SW_EXIT_INFO1 register to indicate no error 929 let mut swei1_rw_gpa_arg = 930 mshv_bindings::mshv_read_write_gpa { 931 base_gpa: ghcb_gpa + GHCB_SW_EXITINFO1_OFFSET, 932 byte_count: std::mem::size_of::<u64>() as u32, 933 ..Default::default() 934 }; 935 self.fd.gpa_write(&mut swei1_rw_gpa_arg).map_err( 936 |e| cpu::HypervisorCpuError::GpaWrite(e.into()), 937 )?; 938 } 939 SVM_NAE_HV_DOORBELL_PAGE_QUERY => { 940 let mut reg_assocs = [ hv_register_assoc { 941 name: hv_register_name_HV_X64_REGISTER_SEV_DOORBELL_GPA, 942 ..Default::default() 943 } ]; 944 self.fd.get_reg(&mut reg_assocs).unwrap(); 945 // SAFETY: Accessing a union element from bindgen generated bindings. 946 let doorbell_gpa = unsafe { reg_assocs[0].value.reg64 }; 947 let mut swei2_rw_gpa_arg = 948 mshv_bindings::mshv_read_write_gpa { 949 base_gpa: ghcb_gpa + GHCB_SW_EXITINFO2_OFFSET, 950 byte_count: std::mem::size_of::<u64>() as u32, 951 ..Default::default() 952 }; 953 swei2_rw_gpa_arg 954 .data 955 .copy_from_slice(&doorbell_gpa.to_le_bytes()); 956 self.fd.gpa_write(&mut swei2_rw_gpa_arg).map_err( 957 |e| cpu::HypervisorCpuError::GpaWrite(e.into()), 958 )?; 959 } 960 SVM_NAE_HV_DOORBELL_PAGE_CLEAR => { 961 let mut swei2_rw_gpa_arg = 962 mshv_bindings::mshv_read_write_gpa { 963 base_gpa: ghcb_gpa + GHCB_SW_EXITINFO2_OFFSET, 964 byte_count: std::mem::size_of::<u64>() as u32, 965 ..Default::default() 966 }; 967 self.fd.gpa_write(&mut swei2_rw_gpa_arg).map_err( 968 |e| cpu::HypervisorCpuError::GpaWrite(e.into()), 969 )?; 970 } 971 _ => { 972 panic!( 973 "SVM_EXITCODE_HV_DOORBELL_PAGE: Unhandled exit code: {:0x}", 974 exit_info1 975 ); 976 } 977 } 978 } 979 SVM_EXITCODE_SNP_EXTENDED_GUEST_REQUEST => { 980 warn!("Fetching extended guest request is not supported"); 981 // Extended guest request is not supported by the Hypervisor 982 // Returning the error to the guest 983 // 0x6 means `The NAE event was not valid` 984 // Reference: GHCB Spec, page 42 985 let value: u64 = 0x6; 986 let mut swei2_rw_gpa_arg = mshv_bindings::mshv_read_write_gpa { 987 base_gpa: ghcb_gpa + GHCB_SW_EXITINFO2_OFFSET, 988 byte_count: std::mem::size_of::<u64>() as u32, 989 ..Default::default() 990 }; 991 swei2_rw_gpa_arg.data.copy_from_slice(&value.to_le_bytes()); 992 self.fd 993 .gpa_write(&mut swei2_rw_gpa_arg) 994 .map_err(|e| cpu::HypervisorCpuError::GpaWrite(e.into()))?; 995 } 996 SVM_EXITCODE_IOIO_PROT => { 997 let exit_info1 = 998 info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_info1 as u32; 999 let port_info = hv_sev_vmgexit_port_info { 1000 as_uint32: exit_info1, 1001 }; 1002 1003 let port = 1004 // SAFETY: Accessing a union element from bindgen generated bindings. 1005 unsafe { port_info.__bindgen_anon_1.intercepted_port() }; 1006 let mut len = 4; 1007 // SAFETY: Accessing a union element from bindgen generated bindings. 1008 unsafe { 1009 if port_info.__bindgen_anon_1.operand_size_16bit() == 1 { 1010 len = 2; 1011 } else if port_info.__bindgen_anon_1.operand_size_8bit() 1012 == 1 1013 { 1014 len = 1; 1015 } 1016 } 1017 let is_write = 1018 // SAFETY: Accessing a union element from bindgen generated bindings. 1019 unsafe { port_info.__bindgen_anon_1.access_type() == 0 }; 1020 let mut rax_rw_gpa_arg: mshv_read_write_gpa = 1021 mshv_bindings::mshv_read_write_gpa { 1022 base_gpa: ghcb_gpa + GHCB_RAX_OFFSET, 1023 byte_count: std::mem::size_of::<u64>() as u32, 1024 ..Default::default() 1025 }; 1026 self.fd 1027 .gpa_read(&mut rax_rw_gpa_arg) 1028 .map_err(|e| cpu::HypervisorCpuError::GpaRead(e.into()))?; 1029 1030 if is_write { 1031 if let Some(vm_ops) = &self.vm_ops { 1032 vm_ops 1033 .pio_write( 1034 port.into(), 1035 &rax_rw_gpa_arg.data[0..len], 1036 ) 1037 .map_err(|e| { 1038 cpu::HypervisorCpuError::RunVcpu(e.into()) 1039 })?; 1040 } 1041 } else { 1042 if let Some(vm_ops) = &self.vm_ops { 1043 vm_ops 1044 .pio_read( 1045 port.into(), 1046 &mut rax_rw_gpa_arg.data[0..len], 1047 ) 1048 .map_err(|e| { 1049 cpu::HypervisorCpuError::RunVcpu(e.into()) 1050 })?; 1051 } 1052 1053 self.fd.gpa_write(&mut rax_rw_gpa_arg).map_err(|e| { 1054 cpu::HypervisorCpuError::GpaWrite(e.into()) 1055 })?; 1056 } 1057 1058 // Clear the SW_EXIT_INFO1 register to indicate no error 1059 let mut swei1_rw_gpa_arg = mshv_bindings::mshv_read_write_gpa { 1060 base_gpa: ghcb_gpa + GHCB_SW_EXITINFO1_OFFSET, 1061 byte_count: std::mem::size_of::<u64>() as u32, 1062 ..Default::default() 1063 }; 1064 self.fd 1065 .gpa_write(&mut swei1_rw_gpa_arg) 1066 .map_err(|e| cpu::HypervisorCpuError::GpaWrite(e.into()))?; 1067 } 1068 SVM_EXITCODE_MMIO_READ => { 1069 let src_gpa = 1070 info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_info1; 1071 let dst_gpa = info.__bindgen_anon_2.__bindgen_anon_1.sw_scratch; 1072 let data_len = 1073 info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_info2 1074 as usize; 1075 // Sanity check to make sure data len is within supported range. 1076 assert!(data_len <= 0x8); 1077 1078 let mut data: Vec<u8> = vec![0; data_len]; 1079 if let Some(vm_ops) = &self.vm_ops { 1080 vm_ops.mmio_read(src_gpa, &mut data[0..data_len]).map_err( 1081 |e| cpu::HypervisorCpuError::RunVcpu(e.into()), 1082 )?; 1083 } 1084 let mut arg: mshv_read_write_gpa = 1085 mshv_bindings::mshv_read_write_gpa { 1086 base_gpa: dst_gpa, 1087 byte_count: data_len as u32, 1088 ..Default::default() 1089 }; 1090 arg.data[0..data_len].copy_from_slice(&data); 1091 1092 self.fd 1093 .gpa_write(&mut arg) 1094 .map_err(|e| cpu::HypervisorCpuError::GpaWrite(e.into()))?; 1095 } 1096 SVM_EXITCODE_MMIO_WRITE => { 1097 let dst_gpa = 1098 info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_info1; 1099 let src_gpa = info.__bindgen_anon_2.__bindgen_anon_1.sw_scratch; 1100 let data_len = 1101 info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_info2 1102 as usize; 1103 // Sanity check to make sure data len is within supported range. 1104 assert!(data_len <= 0x8); 1105 let mut arg: mshv_read_write_gpa = 1106 mshv_bindings::mshv_read_write_gpa { 1107 base_gpa: src_gpa, 1108 byte_count: data_len as u32, 1109 ..Default::default() 1110 }; 1111 1112 self.fd 1113 .gpa_read(&mut arg) 1114 .map_err(|e| cpu::HypervisorCpuError::GpaRead(e.into()))?; 1115 1116 if let Some(vm_ops) = &self.vm_ops { 1117 vm_ops 1118 .mmio_write(dst_gpa, &arg.data[0..data_len]) 1119 .map_err(|e| { 1120 cpu::HypervisorCpuError::RunVcpu(e.into()) 1121 })?; 1122 } 1123 } 1124 SVM_EXITCODE_SNP_GUEST_REQUEST => { 1125 let req_gpa = 1126 info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_info1; 1127 let rsp_gpa = 1128 info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_info2; 1129 1130 let mshv_psp_req = 1131 mshv_issue_psp_guest_request { req_gpa, rsp_gpa }; 1132 self.vm_fd 1133 .psp_issue_guest_request(&mshv_psp_req) 1134 .map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()))?; 1135 1136 debug!( 1137 "SNP guest request: req_gpa {:0x} rsp_gpa {:0x}", 1138 req_gpa, rsp_gpa 1139 ); 1140 1141 let mut swei2_rw_gpa_arg = mshv_bindings::mshv_read_write_gpa { 1142 base_gpa: ghcb_gpa + GHCB_SW_EXITINFO2_OFFSET, 1143 byte_count: std::mem::size_of::<u64>() as u32, 1144 ..Default::default() 1145 }; 1146 self.fd 1147 .gpa_write(&mut swei2_rw_gpa_arg) 1148 .map_err(|e| cpu::HypervisorCpuError::GpaWrite(e.into()))?; 1149 } 1150 SVM_EXITCODE_SNP_AP_CREATION => { 1151 let vmsa_gpa = 1152 info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_info2; 1153 let apic_id = 1154 info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_info1 >> 32; 1155 debug!( 1156 "SNP AP CREATE REQUEST with VMSA GPA {:0x}, and APIC ID {:?}", 1157 vmsa_gpa, apic_id 1158 ); 1159 1160 let mshv_ap_create_req = mshv_sev_snp_ap_create { 1161 vp_id: apic_id, 1162 vmsa_gpa, 1163 }; 1164 self.vm_fd 1165 .sev_snp_ap_create(&mshv_ap_create_req) 1166 .map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()))?; 1167 1168 let mut swei1_rw_gpa_arg = mshv_bindings::mshv_read_write_gpa { 1169 base_gpa: ghcb_gpa + GHCB_SW_EXITINFO1_OFFSET, 1170 byte_count: std::mem::size_of::<u64>() as u32, 1171 ..Default::default() 1172 }; 1173 1174 self.fd 1175 .gpa_write(&mut swei1_rw_gpa_arg) 1176 .map_err(|e| cpu::HypervisorCpuError::GpaWrite(e.into()))?; 1177 } 1178 _ => panic!( 1179 "GHCB_INFO_NORMAL: Unhandled exit code: {:0x}", 1180 exit_code 1181 ), 1182 } 1183 } 1184 _ => panic!("Unsupported VMGEXIT operation: {:0x}", ghcb_op), 1185 } 1186 1187 Ok(cpu::VmExit::Ignore) 1188 } 1189 exit => Err(cpu::HypervisorCpuError::RunVcpu(anyhow!( 1190 "Unhandled VCPU exit {:?}", 1191 exit 1192 ))), 1193 }, 1194 1195 Err(e) => match e.errno() { 1196 libc::EAGAIN | libc::EINTR => Ok(cpu::VmExit::Ignore), 1197 _ => Err(cpu::HypervisorCpuError::RunVcpu(anyhow!( 1198 "VCPU error {:?}", 1199 e 1200 ))), 1201 }, 1202 } 1203 } 1204 1205 #[cfg(target_arch = "aarch64")] 1206 fn init_pmu(&self, irq: u32) -> cpu::Result<()> { 1207 unimplemented!() 1208 } 1209 1210 #[cfg(target_arch = "aarch64")] 1211 fn has_pmu_support(&self) -> bool { 1212 unimplemented!() 1213 } 1214 1215 #[cfg(target_arch = "aarch64")] 1216 fn setup_regs(&self, cpu_id: u8, boot_ip: u64, fdt_start: u64) -> cpu::Result<()> { 1217 unimplemented!() 1218 } 1219 1220 #[cfg(target_arch = "aarch64")] 1221 fn get_sys_reg(&self, sys_reg: u32) -> cpu::Result<u64> { 1222 unimplemented!() 1223 } 1224 1225 #[cfg(target_arch = "aarch64")] 1226 fn get_reg_list(&self, reg_list: &mut RegList) -> cpu::Result<()> { 1227 unimplemented!() 1228 } 1229 1230 #[cfg(target_arch = "aarch64")] 1231 fn vcpu_init(&self, kvi: &VcpuInit) -> cpu::Result<()> { 1232 unimplemented!() 1233 } 1234 1235 #[cfg(target_arch = "aarch64")] 1236 fn set_regs(&self, regs: &StandardRegisters) -> cpu::Result<()> { 1237 unimplemented!() 1238 } 1239 1240 #[cfg(target_arch = "aarch64")] 1241 fn get_regs(&self) -> cpu::Result<StandardRegisters> { 1242 unimplemented!() 1243 } 1244 1245 #[cfg(target_arch = "x86_64")] 1246 /// 1247 /// X86 specific call to setup the CPUID registers. 1248 /// 1249 fn set_cpuid2(&self, cpuid: &[CpuIdEntry]) -> cpu::Result<()> { 1250 let cpuid: Vec<mshv_bindings::hv_cpuid_entry> = cpuid.iter().map(|e| (*e).into()).collect(); 1251 let mshv_cpuid = <CpuId>::from_entries(&cpuid) 1252 .map_err(|_| cpu::HypervisorCpuError::SetCpuid(anyhow!("failed to create CpuId")))?; 1253 1254 self.fd 1255 .register_intercept_result_cpuid(&mshv_cpuid) 1256 .map_err(|e| cpu::HypervisorCpuError::SetCpuid(e.into())) 1257 } 1258 1259 #[cfg(target_arch = "x86_64")] 1260 /// 1261 /// X86 specific call to retrieve the CPUID registers. 1262 /// 1263 fn get_cpuid2(&self, _num_entries: usize) -> cpu::Result<Vec<CpuIdEntry>> { 1264 Ok(self.cpuid.clone()) 1265 } 1266 1267 #[cfg(target_arch = "x86_64")] 1268 /// 1269 /// X86 specific call to retrieve cpuid leaf 1270 /// 1271 fn get_cpuid_values( 1272 &self, 1273 function: u32, 1274 index: u32, 1275 xfem: u64, 1276 xss: u64, 1277 ) -> cpu::Result<[u32; 4]> { 1278 self.fd 1279 .get_cpuid_values(function, index, xfem, xss) 1280 .map_err(|e| cpu::HypervisorCpuError::GetCpuidVales(e.into())) 1281 } 1282 1283 #[cfg(target_arch = "x86_64")] 1284 /// 1285 /// Returns the state of the LAPIC (Local Advanced Programmable Interrupt Controller). 1286 /// 1287 fn get_lapic(&self) -> cpu::Result<crate::arch::x86::LapicState> { 1288 Ok(self 1289 .fd 1290 .get_lapic() 1291 .map_err(|e| cpu::HypervisorCpuError::GetlapicState(e.into()))? 1292 .into()) 1293 } 1294 1295 #[cfg(target_arch = "x86_64")] 1296 /// 1297 /// Sets the state of the LAPIC (Local Advanced Programmable Interrupt Controller). 1298 /// 1299 fn set_lapic(&self, lapic: &crate::arch::x86::LapicState) -> cpu::Result<()> { 1300 let lapic: mshv_bindings::LapicState = (*lapic).clone().into(); 1301 self.fd 1302 .set_lapic(&lapic) 1303 .map_err(|e| cpu::HypervisorCpuError::SetLapicState(e.into())) 1304 } 1305 1306 /// 1307 /// Returns the vcpu's current "multiprocessing state". 1308 /// 1309 fn get_mp_state(&self) -> cpu::Result<MpState> { 1310 Ok(MpState::Mshv) 1311 } 1312 1313 /// 1314 /// Sets the vcpu's current "multiprocessing state". 1315 /// 1316 fn set_mp_state(&self, _mp_state: MpState) -> cpu::Result<()> { 1317 Ok(()) 1318 } 1319 1320 #[cfg(target_arch = "x86_64")] 1321 /// 1322 /// Set CPU state for x86_64 guest. 1323 /// 1324 fn set_state(&self, state: &CpuState) -> cpu::Result<()> { 1325 let mut state: VcpuMshvState = state.clone().into(); 1326 self.set_msrs(&state.msrs)?; 1327 self.set_vcpu_events(&state.vcpu_events)?; 1328 self.set_regs(&state.regs.into())?; 1329 self.set_sregs(&state.sregs.into())?; 1330 self.set_fpu(&state.fpu)?; 1331 self.set_xcrs(&state.xcrs)?; 1332 // These registers are global and needed to be set only for first VCPU 1333 // as Microsoft Hypervisor allows setting this register for only one VCPU 1334 if self.vp_index == 0 { 1335 self.fd 1336 .set_misc_regs(&state.misc) 1337 .map_err(|e| cpu::HypervisorCpuError::SetMiscRegs(e.into()))? 1338 } 1339 self.fd 1340 .set_debug_regs(&state.dbg) 1341 .map_err(|e| cpu::HypervisorCpuError::SetDebugRegs(e.into()))?; 1342 self.fd 1343 .set_all_vp_state_components(&mut state.vp_states) 1344 .map_err(|e| cpu::HypervisorCpuError::SetAllVpStateComponents(e.into()))?; 1345 Ok(()) 1346 } 1347 1348 #[cfg(target_arch = "aarch64")] 1349 /// 1350 /// Set CPU state for aarch64 guest. 1351 /// 1352 fn set_state(&self, state: &CpuState) -> cpu::Result<()> { 1353 unimplemented!() 1354 } 1355 1356 #[cfg(target_arch = "x86_64")] 1357 /// 1358 /// Get CPU State for x86_64 guest 1359 /// 1360 fn state(&self) -> cpu::Result<CpuState> { 1361 let regs = self.get_regs()?; 1362 let sregs = self.get_sregs()?; 1363 let xcrs = self.get_xcrs()?; 1364 let fpu = self.get_fpu()?; 1365 let vcpu_events = self.get_vcpu_events()?; 1366 let mut msrs = self.msrs.clone(); 1367 self.get_msrs(&mut msrs)?; 1368 let misc = self 1369 .fd 1370 .get_misc_regs() 1371 .map_err(|e| cpu::HypervisorCpuError::GetMiscRegs(e.into()))?; 1372 let dbg = self 1373 .fd 1374 .get_debug_regs() 1375 .map_err(|e| cpu::HypervisorCpuError::GetDebugRegs(e.into()))?; 1376 let vp_states = self 1377 .fd 1378 .get_all_vp_state_components() 1379 .map_err(|e| cpu::HypervisorCpuError::GetAllVpStateComponents(e.into()))?; 1380 1381 Ok(VcpuMshvState { 1382 msrs, 1383 vcpu_events, 1384 regs: regs.into(), 1385 sregs: sregs.into(), 1386 fpu, 1387 xcrs, 1388 dbg, 1389 misc, 1390 vp_states, 1391 } 1392 .into()) 1393 } 1394 1395 #[cfg(target_arch = "aarch64")] 1396 /// 1397 /// Get CPU state for aarch64 guest. 1398 /// 1399 fn state(&self) -> cpu::Result<CpuState> { 1400 unimplemented!() 1401 } 1402 1403 #[cfg(target_arch = "x86_64")] 1404 /// 1405 /// Translate guest virtual address to guest physical address 1406 /// 1407 fn translate_gva(&self, gva: u64, flags: u64) -> cpu::Result<(u64, u32)> { 1408 let r = self 1409 .fd 1410 .translate_gva(gva, flags) 1411 .map_err(|e| cpu::HypervisorCpuError::TranslateVirtualAddress(e.into()))?; 1412 1413 let gpa = r.0; 1414 // SAFETY: r is valid, otherwise this function will have returned 1415 let result_code = unsafe { r.1.__bindgen_anon_1.result_code }; 1416 1417 Ok((gpa, result_code)) 1418 } 1419 1420 #[cfg(target_arch = "x86_64")] 1421 /// 1422 /// Return the list of initial MSR entries for a VCPU 1423 /// 1424 fn boot_msr_entries(&self) -> Vec<MsrEntry> { 1425 use crate::arch::x86::{msr_index, MTRR_ENABLE, MTRR_MEM_TYPE_WB}; 1426 1427 [ 1428 msr!(msr_index::MSR_IA32_SYSENTER_CS), 1429 msr!(msr_index::MSR_IA32_SYSENTER_ESP), 1430 msr!(msr_index::MSR_IA32_SYSENTER_EIP), 1431 msr!(msr_index::MSR_STAR), 1432 msr!(msr_index::MSR_CSTAR), 1433 msr!(msr_index::MSR_LSTAR), 1434 msr!(msr_index::MSR_KERNEL_GS_BASE), 1435 msr!(msr_index::MSR_SYSCALL_MASK), 1436 msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB), 1437 ] 1438 .to_vec() 1439 } 1440 1441 /// 1442 /// Sets the AMD specific vcpu's sev control register. 1443 /// 1444 #[cfg(feature = "sev_snp")] 1445 fn set_sev_control_register(&self, vmsa_pfn: u64) -> cpu::Result<()> { 1446 let sev_control_reg = snp::get_sev_control_register(vmsa_pfn); 1447 1448 self.fd 1449 .set_sev_control_register(sev_control_reg) 1450 .map_err(|e| cpu::HypervisorCpuError::SetSevControlRegister(e.into())) 1451 } 1452 #[cfg(target_arch = "x86_64")] 1453 /// 1454 /// Trigger NMI interrupt 1455 /// 1456 fn nmi(&self) -> cpu::Result<()> { 1457 let cfg = InterruptRequest { 1458 interrupt_type: hv_interrupt_type_HV_X64_INTERRUPT_TYPE_NMI, 1459 apic_id: self.vp_index as u64, 1460 level_triggered: false, 1461 vector: 0, 1462 logical_destination_mode: false, 1463 long_mode: false, 1464 }; 1465 self.vm_fd 1466 .request_virtual_interrupt(&cfg) 1467 .map_err(|e| cpu::HypervisorCpuError::Nmi(e.into())) 1468 } 1469 } 1470 1471 impl MshvVcpu { 1472 #[cfg(target_arch = "x86_64")] 1473 /// 1474 /// X86 specific call that returns the vcpu's current "xcrs". 1475 /// 1476 fn get_xcrs(&self) -> cpu::Result<ExtendedControlRegisters> { 1477 self.fd 1478 .get_xcrs() 1479 .map_err(|e| cpu::HypervisorCpuError::GetXcsr(e.into())) 1480 } 1481 1482 #[cfg(target_arch = "x86_64")] 1483 /// 1484 /// X86 specific call that sets the vcpu's current "xcrs". 1485 /// 1486 fn set_xcrs(&self, xcrs: &ExtendedControlRegisters) -> cpu::Result<()> { 1487 self.fd 1488 .set_xcrs(xcrs) 1489 .map_err(|e| cpu::HypervisorCpuError::SetXcsr(e.into())) 1490 } 1491 1492 #[cfg(target_arch = "x86_64")] 1493 /// 1494 /// Returns currently pending exceptions, interrupts, and NMIs as well as related 1495 /// states of the vcpu. 1496 /// 1497 fn get_vcpu_events(&self) -> cpu::Result<VcpuEvents> { 1498 self.fd 1499 .get_vcpu_events() 1500 .map_err(|e| cpu::HypervisorCpuError::GetVcpuEvents(e.into())) 1501 } 1502 1503 #[cfg(target_arch = "x86_64")] 1504 /// 1505 /// Sets pending exceptions, interrupts, and NMIs as well as related states 1506 /// of the vcpu. 1507 /// 1508 fn set_vcpu_events(&self, events: &VcpuEvents) -> cpu::Result<()> { 1509 self.fd 1510 .set_vcpu_events(events) 1511 .map_err(|e| cpu::HypervisorCpuError::SetVcpuEvents(e.into())) 1512 } 1513 } 1514 1515 /// Wrapper over Mshv VM ioctls. 1516 pub struct MshvVm { 1517 fd: Arc<VmFd>, 1518 #[cfg(target_arch = "x86_64")] 1519 msrs: Vec<MsrEntry>, 1520 dirty_log_slots: Arc<RwLock<HashMap<u64, MshvDirtyLogSlot>>>, 1521 #[cfg(feature = "sev_snp")] 1522 sev_snp_enabled: bool, 1523 } 1524 1525 impl MshvVm { 1526 /// 1527 /// Creates an in-kernel device. 1528 /// 1529 /// See the documentation for `MSHV_CREATE_DEVICE`. 1530 fn create_device(&self, device: &mut CreateDevice) -> vm::Result<VfioDeviceFd> { 1531 let device_fd = self 1532 .fd 1533 .create_device(device) 1534 .map_err(|e| vm::HypervisorVmError::CreateDevice(e.into()))?; 1535 Ok(VfioDeviceFd::new_from_mshv(device_fd)) 1536 } 1537 } 1538 1539 /// 1540 /// Implementation of Vm trait for Mshv 1541 /// 1542 /// # Examples 1543 /// 1544 /// ``` 1545 /// # extern crate hypervisor; 1546 /// # use hypervisor::mshv::MshvHypervisor; 1547 /// # use std::sync::Arc; 1548 /// let mshv = MshvHypervisor::new().unwrap(); 1549 /// let hypervisor = Arc::new(mshv); 1550 /// let vm = hypervisor.create_vm().expect("new VM fd creation failed"); 1551 /// ``` 1552 impl vm::Vm for MshvVm { 1553 #[cfg(target_arch = "x86_64")] 1554 /// 1555 /// Sets the address of the one-page region in the VM's address space. 1556 /// 1557 fn set_identity_map_address(&self, _address: u64) -> vm::Result<()> { 1558 Ok(()) 1559 } 1560 1561 #[cfg(target_arch = "x86_64")] 1562 /// 1563 /// Sets the address of the three-page region in the VM's address space. 1564 /// 1565 fn set_tss_address(&self, _offset: usize) -> vm::Result<()> { 1566 Ok(()) 1567 } 1568 1569 /// 1570 /// Creates an in-kernel interrupt controller. 1571 /// 1572 fn create_irq_chip(&self) -> vm::Result<()> { 1573 Ok(()) 1574 } 1575 1576 /// 1577 /// Registers an event that will, when signaled, trigger the `gsi` IRQ. 1578 /// 1579 fn register_irqfd(&self, fd: &EventFd, gsi: u32) -> vm::Result<()> { 1580 debug!("register_irqfd fd {} gsi {}", fd.as_raw_fd(), gsi); 1581 1582 self.fd 1583 .register_irqfd(fd, gsi) 1584 .map_err(|e| vm::HypervisorVmError::RegisterIrqFd(e.into()))?; 1585 1586 Ok(()) 1587 } 1588 1589 /// 1590 /// Unregisters an event that will, when signaled, trigger the `gsi` IRQ. 1591 /// 1592 fn unregister_irqfd(&self, fd: &EventFd, gsi: u32) -> vm::Result<()> { 1593 debug!("unregister_irqfd fd {} gsi {}", fd.as_raw_fd(), gsi); 1594 1595 self.fd 1596 .unregister_irqfd(fd, gsi) 1597 .map_err(|e| vm::HypervisorVmError::UnregisterIrqFd(e.into()))?; 1598 1599 Ok(()) 1600 } 1601 1602 /// 1603 /// Creates a VcpuFd object from a vcpu RawFd. 1604 /// 1605 fn create_vcpu( 1606 &self, 1607 id: u8, 1608 vm_ops: Option<Arc<dyn VmOps>>, 1609 ) -> vm::Result<Arc<dyn cpu::Vcpu>> { 1610 let vcpu_fd = self 1611 .fd 1612 .create_vcpu(id) 1613 .map_err(|e| vm::HypervisorVmError::CreateVcpu(e.into()))?; 1614 let vcpu = MshvVcpu { 1615 fd: vcpu_fd, 1616 vp_index: id, 1617 #[cfg(target_arch = "x86_64")] 1618 cpuid: Vec::new(), 1619 #[cfg(target_arch = "x86_64")] 1620 msrs: self.msrs.clone(), 1621 vm_ops, 1622 vm_fd: self.fd.clone(), 1623 }; 1624 Ok(Arc::new(vcpu)) 1625 } 1626 1627 #[cfg(target_arch = "x86_64")] 1628 fn enable_split_irq(&self) -> vm::Result<()> { 1629 Ok(()) 1630 } 1631 1632 #[cfg(target_arch = "x86_64")] 1633 fn enable_sgx_attribute(&self, _file: File) -> vm::Result<()> { 1634 Ok(()) 1635 } 1636 1637 fn register_ioevent( 1638 &self, 1639 fd: &EventFd, 1640 addr: &IoEventAddress, 1641 datamatch: Option<DataMatch>, 1642 ) -> vm::Result<()> { 1643 #[cfg(feature = "sev_snp")] 1644 if self.sev_snp_enabled { 1645 return Ok(()); 1646 } 1647 1648 let addr = &mshv_ioctls::IoEventAddress::from(*addr); 1649 debug!( 1650 "register_ioevent fd {} addr {:x?} datamatch {:?}", 1651 fd.as_raw_fd(), 1652 addr, 1653 datamatch 1654 ); 1655 if let Some(dm) = datamatch { 1656 match dm { 1657 vm::DataMatch::DataMatch32(mshv_dm32) => self 1658 .fd 1659 .register_ioevent(fd, addr, mshv_dm32) 1660 .map_err(|e| vm::HypervisorVmError::RegisterIoEvent(e.into())), 1661 vm::DataMatch::DataMatch64(mshv_dm64) => self 1662 .fd 1663 .register_ioevent(fd, addr, mshv_dm64) 1664 .map_err(|e| vm::HypervisorVmError::RegisterIoEvent(e.into())), 1665 } 1666 } else { 1667 self.fd 1668 .register_ioevent(fd, addr, NoDatamatch) 1669 .map_err(|e| vm::HypervisorVmError::RegisterIoEvent(e.into())) 1670 } 1671 } 1672 1673 /// Unregister an event from a certain address it has been previously registered to. 1674 fn unregister_ioevent(&self, fd: &EventFd, addr: &IoEventAddress) -> vm::Result<()> { 1675 #[cfg(feature = "sev_snp")] 1676 if self.sev_snp_enabled { 1677 return Ok(()); 1678 } 1679 1680 let addr = &mshv_ioctls::IoEventAddress::from(*addr); 1681 debug!("unregister_ioevent fd {} addr {:x?}", fd.as_raw_fd(), addr); 1682 1683 self.fd 1684 .unregister_ioevent(fd, addr, NoDatamatch) 1685 .map_err(|e| vm::HypervisorVmError::UnregisterIoEvent(e.into())) 1686 } 1687 1688 /// Creates a guest physical memory region. 1689 fn create_user_memory_region(&self, user_memory_region: UserMemoryRegion) -> vm::Result<()> { 1690 let user_memory_region: mshv_user_mem_region = user_memory_region.into(); 1691 // No matter read only or not we keep track the slots. 1692 // For readonly hypervisor can enable the dirty bits, 1693 // but a VM exit happens before setting the dirty bits 1694 self.dirty_log_slots.write().unwrap().insert( 1695 user_memory_region.guest_pfn, 1696 MshvDirtyLogSlot { 1697 guest_pfn: user_memory_region.guest_pfn, 1698 memory_size: user_memory_region.size, 1699 }, 1700 ); 1701 1702 self.fd 1703 .map_user_memory(user_memory_region) 1704 .map_err(|e| vm::HypervisorVmError::CreateUserMemory(e.into()))?; 1705 Ok(()) 1706 } 1707 1708 /// Removes a guest physical memory region. 1709 fn remove_user_memory_region(&self, user_memory_region: UserMemoryRegion) -> vm::Result<()> { 1710 let user_memory_region: mshv_user_mem_region = user_memory_region.into(); 1711 // Remove the corresponding entry from "self.dirty_log_slots" if needed 1712 self.dirty_log_slots 1713 .write() 1714 .unwrap() 1715 .remove(&user_memory_region.guest_pfn); 1716 1717 self.fd 1718 .unmap_user_memory(user_memory_region) 1719 .map_err(|e| vm::HypervisorVmError::RemoveUserMemory(e.into()))?; 1720 Ok(()) 1721 } 1722 1723 fn make_user_memory_region( 1724 &self, 1725 _slot: u32, 1726 guest_phys_addr: u64, 1727 memory_size: u64, 1728 userspace_addr: u64, 1729 readonly: bool, 1730 _log_dirty_pages: bool, 1731 ) -> UserMemoryRegion { 1732 let mut flags = HV_MAP_GPA_READABLE | HV_MAP_GPA_EXECUTABLE | HV_MAP_GPA_ADJUSTABLE; 1733 if !readonly { 1734 flags |= HV_MAP_GPA_WRITABLE; 1735 } 1736 1737 mshv_user_mem_region { 1738 flags, 1739 guest_pfn: guest_phys_addr >> PAGE_SHIFT, 1740 size: memory_size, 1741 userspace_addr, 1742 } 1743 .into() 1744 } 1745 1746 fn create_passthrough_device(&self) -> vm::Result<VfioDeviceFd> { 1747 let mut vfio_dev = mshv_create_device { 1748 type_: mshv_device_type_MSHV_DEV_TYPE_VFIO, 1749 fd: 0, 1750 flags: 0, 1751 }; 1752 1753 self.create_device(&mut vfio_dev) 1754 .map_err(|e| vm::HypervisorVmError::CreatePassthroughDevice(e.into())) 1755 } 1756 1757 /// 1758 /// Constructs a routing entry 1759 /// 1760 fn make_routing_entry(&self, gsi: u32, config: &InterruptSourceConfig) -> IrqRoutingEntry { 1761 match config { 1762 InterruptSourceConfig::MsiIrq(cfg) => mshv_msi_routing_entry { 1763 gsi, 1764 address_lo: cfg.low_addr, 1765 address_hi: cfg.high_addr, 1766 data: cfg.data, 1767 } 1768 .into(), 1769 _ => { 1770 unreachable!() 1771 } 1772 } 1773 } 1774 1775 fn set_gsi_routing(&self, entries: &[IrqRoutingEntry]) -> vm::Result<()> { 1776 let mut msi_routing = 1777 vec_with_array_field::<mshv_msi_routing, mshv_msi_routing_entry>(entries.len()); 1778 msi_routing[0].nr = entries.len() as u32; 1779 1780 let entries: Vec<mshv_msi_routing_entry> = entries 1781 .iter() 1782 .map(|entry| match entry { 1783 IrqRoutingEntry::Mshv(e) => *e, 1784 #[allow(unreachable_patterns)] 1785 _ => panic!("IrqRoutingEntry type is wrong"), 1786 }) 1787 .collect(); 1788 1789 // SAFETY: msi_routing initialized with entries.len() and now it is being turned into 1790 // entries_slice with entries.len() again. It is guaranteed to be large enough to hold 1791 // everything from entries. 1792 unsafe { 1793 let entries_slice: &mut [mshv_msi_routing_entry] = 1794 msi_routing[0].entries.as_mut_slice(entries.len()); 1795 entries_slice.copy_from_slice(&entries); 1796 } 1797 1798 self.fd 1799 .set_msi_routing(&msi_routing[0]) 1800 .map_err(|e| vm::HypervisorVmError::SetGsiRouting(e.into())) 1801 } 1802 1803 /// 1804 /// Start logging dirty pages 1805 /// 1806 fn start_dirty_log(&self) -> vm::Result<()> { 1807 self.fd 1808 .enable_dirty_page_tracking() 1809 .map_err(|e| vm::HypervisorVmError::StartDirtyLog(e.into())) 1810 } 1811 1812 /// 1813 /// Stop logging dirty pages 1814 /// 1815 fn stop_dirty_log(&self) -> vm::Result<()> { 1816 let dirty_log_slots = self.dirty_log_slots.read().unwrap(); 1817 // Before disabling the dirty page tracking we need 1818 // to set the dirty bits in the Hypervisor 1819 // This is a requirement from Microsoft Hypervisor 1820 for (_, s) in dirty_log_slots.iter() { 1821 self.fd 1822 .get_dirty_log(s.guest_pfn, s.memory_size as usize, DIRTY_BITMAP_SET_DIRTY) 1823 .map_err(|e| vm::HypervisorVmError::StartDirtyLog(e.into()))?; 1824 } 1825 self.fd 1826 .disable_dirty_page_tracking() 1827 .map_err(|e| vm::HypervisorVmError::StartDirtyLog(e.into()))?; 1828 Ok(()) 1829 } 1830 1831 /// 1832 /// Get dirty pages bitmap (one bit per page) 1833 /// 1834 fn get_dirty_log(&self, _slot: u32, base_gpa: u64, memory_size: u64) -> vm::Result<Vec<u64>> { 1835 self.fd 1836 .get_dirty_log( 1837 base_gpa >> PAGE_SHIFT, 1838 memory_size as usize, 1839 DIRTY_BITMAP_CLEAR_DIRTY, 1840 ) 1841 .map_err(|e| vm::HypervisorVmError::GetDirtyLog(e.into())) 1842 } 1843 1844 /// Retrieve guest clock. 1845 #[cfg(target_arch = "x86_64")] 1846 fn get_clock(&self) -> vm::Result<ClockData> { 1847 let val = self 1848 .fd 1849 .get_partition_property(hv_partition_property_code_HV_PARTITION_PROPERTY_REFERENCE_TIME) 1850 .map_err(|e| vm::HypervisorVmError::GetClock(e.into()))?; 1851 Ok(MshvClockData { ref_time: val }.into()) 1852 } 1853 1854 /// Set guest clock. 1855 #[cfg(target_arch = "x86_64")] 1856 fn set_clock(&self, data: &ClockData) -> vm::Result<()> { 1857 let data: MshvClockData = (*data).into(); 1858 self.fd 1859 .set_partition_property( 1860 hv_partition_property_code_HV_PARTITION_PROPERTY_REFERENCE_TIME, 1861 data.ref_time, 1862 ) 1863 .map_err(|e| vm::HypervisorVmError::SetClock(e.into())) 1864 } 1865 1866 /// Downcast to the underlying MshvVm type 1867 fn as_any(&self) -> &dyn Any { 1868 self 1869 } 1870 1871 /// Initialize the SEV-SNP VM 1872 #[cfg(feature = "sev_snp")] 1873 fn sev_snp_init(&self) -> vm::Result<()> { 1874 self.fd 1875 .set_partition_property( 1876 hv_partition_property_code_HV_PARTITION_PROPERTY_ISOLATION_STATE, 1877 hv_partition_isolation_state_HV_PARTITION_ISOLATION_SECURE as u64, 1878 ) 1879 .map_err(|e| vm::HypervisorVmError::InitializeSevSnp(e.into())) 1880 } 1881 1882 /// 1883 /// Importing isolated pages, these pages will be used 1884 /// for the PSP(Platform Security Processor) measurement. 1885 #[cfg(feature = "sev_snp")] 1886 fn import_isolated_pages( 1887 &self, 1888 page_type: u32, 1889 page_size: u32, 1890 pages: &[u64], 1891 ) -> vm::Result<()> { 1892 if pages.is_empty() { 1893 return Ok(()); 1894 } 1895 1896 let mut isolated_pages = 1897 vec_with_array_field::<mshv_import_isolated_pages, u64>(pages.len()); 1898 isolated_pages[0].num_pages = pages.len() as u64; 1899 isolated_pages[0].page_type = page_type; 1900 isolated_pages[0].page_size = page_size; 1901 // SAFETY: isolated_pages initialized with pages.len() and now it is being turned into 1902 // pages_slice with pages.len() again. It is guaranteed to be large enough to hold 1903 // everything from pages. 1904 unsafe { 1905 let pages_slice: &mut [u64] = isolated_pages[0].page_number.as_mut_slice(pages.len()); 1906 pages_slice.copy_from_slice(pages); 1907 } 1908 self.fd 1909 .import_isolated_pages(&isolated_pages[0]) 1910 .map_err(|e| vm::HypervisorVmError::ImportIsolatedPages(e.into())) 1911 } 1912 1913 /// 1914 /// Complete isolated import, telling the hypervisor that 1915 /// importing the pages to guest memory is complete. 1916 /// 1917 #[cfg(feature = "sev_snp")] 1918 fn complete_isolated_import( 1919 &self, 1920 snp_id_block: IGVM_VHS_SNP_ID_BLOCK, 1921 host_data: [u8; 32], 1922 id_block_enabled: u8, 1923 ) -> vm::Result<()> { 1924 let mut auth_info = hv_snp_id_auth_info { 1925 id_key_algorithm: snp_id_block.id_key_algorithm, 1926 auth_key_algorithm: snp_id_block.author_key_algorithm, 1927 ..Default::default() 1928 }; 1929 // Each of r/s component is 576 bits long 1930 auth_info.id_block_signature[..SIG_R_COMPONENT_SIZE_IN_BYTES] 1931 .copy_from_slice(snp_id_block.id_key_signature.r_comp.as_ref()); 1932 auth_info.id_block_signature 1933 [SIG_R_COMPONENT_SIZE_IN_BYTES..SIG_R_AND_S_COMPONENT_SIZE_IN_BYTES] 1934 .copy_from_slice(snp_id_block.id_key_signature.s_comp.as_ref()); 1935 auth_info.id_key[..ECDSA_CURVE_ID_SIZE_IN_BYTES] 1936 .copy_from_slice(snp_id_block.id_public_key.curve.to_le_bytes().as_ref()); 1937 auth_info.id_key[ECDSA_SIG_X_COMPONENT_START..ECDSA_SIG_X_COMPONENT_END] 1938 .copy_from_slice(snp_id_block.id_public_key.qx.as_ref()); 1939 auth_info.id_key[ECDSA_SIG_Y_COMPONENT_START..ECDSA_SIG_Y_COMPONENT_END] 1940 .copy_from_slice(snp_id_block.id_public_key.qy.as_ref()); 1941 1942 let data = mshv_complete_isolated_import { 1943 import_data: hv_partition_complete_isolated_import_data { 1944 psp_parameters: hv_psp_launch_finish_data { 1945 id_block: hv_snp_id_block { 1946 launch_digest: snp_id_block.ld, 1947 family_id: snp_id_block.family_id, 1948 image_id: snp_id_block.image_id, 1949 version: snp_id_block.version, 1950 guest_svn: snp_id_block.guest_svn, 1951 policy: get_default_snp_guest_policy(), 1952 }, 1953 id_auth_info: auth_info, 1954 host_data, 1955 id_block_enabled, 1956 author_key_enabled: 0, 1957 }, 1958 }, 1959 }; 1960 self.fd 1961 .complete_isolated_import(&data) 1962 .map_err(|e| vm::HypervisorVmError::CompleteIsolatedImport(e.into())) 1963 } 1964 1965 #[cfg(target_arch = "aarch64")] 1966 fn create_vgic(&self, config: VgicConfig) -> vm::Result<Arc<Mutex<dyn Vgic>>> { 1967 unimplemented!() 1968 } 1969 1970 #[cfg(target_arch = "aarch64")] 1971 fn get_preferred_target(&self, kvi: &mut VcpuInit) -> vm::Result<()> { 1972 unimplemented!() 1973 } 1974 1975 /// Pause the VM 1976 fn pause(&self) -> vm::Result<()> { 1977 // Freeze the partition 1978 self.fd 1979 .set_partition_property( 1980 hv_partition_property_code_HV_PARTITION_PROPERTY_TIME_FREEZE, 1981 1u64, 1982 ) 1983 .map_err(|e| { 1984 vm::HypervisorVmError::SetVmProperty(anyhow!( 1985 "Failed to set partition property: {}", 1986 e 1987 )) 1988 }) 1989 } 1990 1991 /// Resume the VM 1992 fn resume(&self) -> vm::Result<()> { 1993 // Resuming the partition using TIME_FREEZE property 1994 self.fd 1995 .set_partition_property( 1996 hv_partition_property_code_HV_PARTITION_PROPERTY_TIME_FREEZE, 1997 0u64, 1998 ) 1999 .map_err(|e| { 2000 vm::HypervisorVmError::SetVmProperty(anyhow!( 2001 "Failed to set partition property: {}", 2002 e 2003 )) 2004 }) 2005 } 2006 } 2007