1b3a1f5f1SSamuel Ortiz // 2b3a1f5f1SSamuel Ortiz // Copyright © 2020 Intel Corporation 3b3a1f5f1SSamuel Ortiz // 4b3a1f5f1SSamuel Ortiz // SPDX-License-Identifier: Apache-2.0 5b3a1f5f1SSamuel Ortiz // 6b3a1f5f1SSamuel Ortiz 7b3a1f5f1SSamuel Ortiz // EFER (technically not a register) bits 8b3a1f5f1SSamuel Ortiz pub const EFER_LMA: u64 = 0x400; 9b3a1f5f1SSamuel Ortiz pub const EFER_LME: u64 = 0x100; 10b3a1f5f1SSamuel Ortiz 11b3a1f5f1SSamuel Ortiz // CR0 bits 12b3a1f5f1SSamuel Ortiz pub const CR0_PE: u64 = 0x1; 13b3a1f5f1SSamuel Ortiz pub const CR0_PG: u64 = 0x80000000; 14b3a1f5f1SSamuel Ortiz 15b3a1f5f1SSamuel Ortiz // CR4 bits 16b3a1f5f1SSamuel Ortiz pub const CR4_PAE: u64 = 0x20; 17b3a1f5f1SSamuel Ortiz pub const CR4_LA57: u64 = 0x1000; 186d38612fSWei Liu 196d38612fSWei Liu // RFlags bits 206d38612fSWei Liu pub const CF_SHIFT: usize = 0; 216d38612fSWei Liu pub const PF_SHIFT: usize = 2; 226d38612fSWei Liu pub const AF_SHIFT: usize = 4; 236d38612fSWei Liu pub const ZF_SHIFT: usize = 6; 246d38612fSWei Liu pub const SF_SHIFT: usize = 7; 25*e22b6ec7SWei Liu pub const DF_SHIFT: usize = 10; 266d38612fSWei Liu pub const OF_SHIFT: usize = 11; 276d38612fSWei Liu 286d38612fSWei Liu pub const CF: u64 = 1 << CF_SHIFT; 296d38612fSWei Liu pub const PF: u64 = 1 << PF_SHIFT; 306d38612fSWei Liu pub const AF: u64 = 1 << AF_SHIFT; 316d38612fSWei Liu pub const ZF: u64 = 1 << ZF_SHIFT; 326d38612fSWei Liu pub const SF: u64 = 1 << SF_SHIFT; 33*e22b6ec7SWei Liu pub const DF: u64 = 1 << DF_SHIFT; 346d38612fSWei Liu pub const OF: u64 = 1 << OF_SHIFT; 35