1 // 2 // Copyright © 2020 Intel Corporation 3 // 4 // SPDX-License-Identifier: Apache-2.0 5 // 6 7 extern crate iced_x86; 8 9 use crate::arch::emulator::{EmulationError, EmulationResult, PlatformEmulator, PlatformError}; 10 use crate::arch::x86::emulator::instructions::*; 11 use crate::arch::x86::regs::*; 12 use crate::arch::x86::*; 13 use crate::arch::x86::{Exception, SegmentRegisterOps}; 14 use crate::x86_64::{SegmentRegister, SpecialRegisters, StandardRegisters}; 15 use iced_x86::*; 16 17 #[macro_use] 18 mod instructions; 19 20 /// x86 CPU modes 21 #[derive(Debug, PartialEq)] 22 pub enum CpuMode { 23 /// Real mode 24 Real, 25 26 /// Virtual 8086 mode 27 Virtual8086, 28 29 /// 16-bit protected mode 30 Protected16, 31 32 /// 32-bit protected mode 33 Protected, 34 35 /// 64-bit mode, a.k.a. long mode 36 Long, 37 } 38 39 /// CpuStateManager manages an x86 CPU state. 40 /// 41 /// Instruction emulation handlers get a mutable reference to 42 /// a `CpuStateManager` implementation, representing the current state of the 43 /// CPU they have to emulate an instruction stream against. Usually those 44 /// handlers will modify the CPU state by modifying `CpuState` and it is up to 45 /// the handler caller to commit those changes back by invoking a 46 /// `PlatformEmulator` implementation `set_state()` method. 47 /// 48 pub trait CpuStateManager: Clone { 49 /// Reads a CPU register. 50 /// 51 /// # Arguments 52 /// 53 /// * `reg` - A general purpose, control or debug register. 54 fn read_reg(&self, reg: Register) -> Result<u64, PlatformError>; 55 56 /// Write to a CPU register. 57 /// 58 /// # Arguments 59 /// 60 /// * `reg` - A general purpose, control or debug register. 61 /// * `val` - The value to load. 62 fn write_reg(&mut self, reg: Register, val: u64) -> Result<(), PlatformError>; 63 64 /// Reads a segment register. 65 /// 66 /// # Arguments 67 /// 68 /// * `reg` - A segment register. 69 fn read_segment(&self, reg: Register) -> Result<SegmentRegister, PlatformError>; 70 71 /// Write to a segment register. 72 /// 73 /// # Arguments 74 /// 75 /// * `reg` - A segment register. 76 /// * `segment_reg` - The segment register value to load. 77 fn write_segment( 78 &mut self, 79 reg: Register, 80 segment_reg: SegmentRegister, 81 ) -> Result<(), PlatformError>; 82 83 /// Get the CPU instruction pointer. 84 fn ip(&self) -> u64; 85 86 /// Set the CPU instruction pointer. 87 /// 88 /// # Arguments 89 /// 90 /// * `ip` - The CPU instruction pointer. 91 fn set_ip(&mut self, ip: u64); 92 93 /// Get the CPU Extended Feature Enable Register. 94 fn efer(&self) -> u64; 95 96 /// Set the CPU Extended Feature Enable Register. 97 /// 98 /// # Arguments 99 /// 100 /// * `efer` - The CPU EFER value. 101 fn set_efer(&mut self, efer: u64); 102 103 /// Get the CPU flags. 104 fn flags(&self) -> u64; 105 106 /// Set the CPU flags. 107 /// 108 /// # Arguments 109 /// 110 /// * `flags` - The CPU flags 111 fn set_flags(&mut self, flags: u64); 112 113 /// Get the CPU mode. 114 fn mode(&self) -> Result<CpuMode, PlatformError>; 115 116 /// Translate a logical (segmented) address into a linear (virtual) one. 117 /// 118 /// # Arguments 119 /// 120 /// * `segment` - Which segment to use for linearization 121 /// * `logical_addr` - The logical address to be translated 122 fn linearize( 123 &self, 124 segment: Register, 125 logical_addr: u64, 126 write: bool, 127 ) -> Result<u64, PlatformError> { 128 let segment_register = self.read_segment(segment)?; 129 let mode = self.mode()?; 130 131 match mode { 132 CpuMode::Long => { 133 // TODO Check that we got a canonical address. 134 Ok(logical_addr 135 .checked_add(segment_register.base) 136 .ok_or_else(|| { 137 PlatformError::InvalidAddress(anyhow!( 138 "Logical address {:#x} can not be linearized with segment {:#x?}", 139 logical_addr, 140 segment_register 141 )) 142 })?) 143 } 144 145 CpuMode::Protected | CpuMode::Real => { 146 let segment_type = segment_register.segment_type(); 147 148 // Must not write to a read-only segment. 149 if segment_type_ro(segment_type) && write { 150 return Err(PlatformError::InvalidAddress(anyhow!( 151 "Can not write to a read-only segment" 152 ))); 153 } 154 155 let logical_addr = logical_addr & 0xffff_ffffu64; 156 let mut segment_limit: u32 = if segment_register.granularity() != 0 { 157 (segment_register.limit << 12) | 0xfff 158 } else { 159 segment_register.limit 160 }; 161 162 // Expand-down segment 163 if segment_type_expand_down(segment_type) { 164 if logical_addr >= segment_limit.into() { 165 return Err(PlatformError::InvalidAddress(anyhow!( 166 "{:#x} is off limits {:#x} (expand down)", 167 logical_addr, 168 segment_limit 169 ))); 170 } 171 172 if segment_register.db() != 0 { 173 segment_limit = 0xffffffff 174 } else { 175 segment_limit = 0xffff 176 } 177 } 178 179 if logical_addr > segment_limit.into() { 180 return Err(PlatformError::InvalidAddress(anyhow!( 181 "{:#x} is off limits {:#x}", 182 logical_addr, 183 segment_limit 184 ))); 185 } 186 187 Ok(logical_addr + segment_register.base) 188 } 189 190 _ => Err(PlatformError::UnsupportedCpuMode(anyhow!("{:?}", mode))), 191 } 192 } 193 } 194 195 const REGISTER_MASK_64: u64 = 0xffff_ffff_ffff_ffffu64; 196 const REGISTER_MASK_32: u64 = 0xffff_ffffu64; 197 const REGISTER_MASK_16: u64 = 0xffffu64; 198 const REGISTER_MASK_8: u64 = 0xffu64; 199 200 macro_rules! set_reg { 201 ($reg:expr, $mask:expr, $value:expr) => { 202 $reg = ($reg & $mask) | $value 203 }; 204 } 205 206 #[derive(Clone, Default, Debug)] 207 /// A minimal, emulated CPU state. 208 /// 209 /// Hypervisors needing x86 emulation can choose to either use their own 210 /// CPU state structures and implement the CpuStateManager interface for it, 211 /// or use `EmulatorCpuState`. The latter implies creating a new state 212 /// `EmulatorCpuState` instance for each platform `cpu_state()` call, which 213 /// might be less efficient. 214 pub struct EmulatorCpuState { 215 pub regs: StandardRegisters, 216 pub sregs: SpecialRegisters, 217 } 218 219 impl CpuStateManager for EmulatorCpuState { 220 fn read_reg(&self, reg: Register) -> Result<u64, PlatformError> { 221 let mut reg_value: u64 = match reg { 222 Register::RAX | Register::EAX | Register::AX | Register::AL | Register::AH => { 223 self.regs.rax 224 } 225 Register::RBX | Register::EBX | Register::BX | Register::BL | Register::BH => { 226 self.regs.rbx 227 } 228 Register::RCX | Register::ECX | Register::CX | Register::CL | Register::CH => { 229 self.regs.rcx 230 } 231 Register::RDX | Register::EDX | Register::DX | Register::DL | Register::DH => { 232 self.regs.rdx 233 } 234 Register::RSP | Register::ESP | Register::SP => self.regs.rsp, 235 Register::RBP | Register::EBP | Register::BP => self.regs.rbp, 236 Register::RSI | Register::ESI | Register::SI | Register::SIL => self.regs.rsi, 237 Register::RDI | Register::EDI | Register::DI | Register::DIL => self.regs.rdi, 238 Register::R8 | Register::R8D | Register::R8W | Register::R8L => self.regs.r8, 239 Register::R9 | Register::R9D | Register::R9W | Register::R9L => self.regs.r9, 240 Register::R10 | Register::R10D | Register::R10W | Register::R10L => self.regs.r10, 241 Register::R11 | Register::R11D | Register::R11W | Register::R11L => self.regs.r11, 242 Register::R12 | Register::R12D | Register::R12W | Register::R12L => self.regs.r12, 243 Register::R13 | Register::R13D | Register::R13W | Register::R13L => self.regs.r13, 244 Register::R14 | Register::R14D | Register::R14W | Register::R14L => self.regs.r14, 245 Register::R15 | Register::R15D | Register::R15W | Register::R15L => self.regs.r15, 246 Register::CR0 => self.sregs.cr0, 247 Register::CR2 => self.sregs.cr2, 248 Register::CR3 => self.sregs.cr3, 249 Register::CR4 => self.sregs.cr4, 250 Register::CR8 => self.sregs.cr8, 251 252 r => { 253 return Err(PlatformError::InvalidRegister(anyhow!( 254 "read_reg invalid GPR {:?}", 255 r 256 ))) 257 } 258 }; 259 260 reg_value = if reg.is_gpr64() || reg.is_cr() { 261 reg_value 262 } else if reg.is_gpr32() { 263 reg_value & REGISTER_MASK_32 264 } else if reg.is_gpr16() { 265 reg_value & REGISTER_MASK_16 266 } else if reg.is_gpr8() { 267 if reg == Register::AH 268 || reg == Register::BH 269 || reg == Register::CH 270 || reg == Register::DH 271 { 272 (reg_value >> 8) & REGISTER_MASK_8 273 } else { 274 reg_value & REGISTER_MASK_8 275 } 276 } else { 277 return Err(PlatformError::InvalidRegister(anyhow!( 278 "read_reg invalid GPR {:?}", 279 reg 280 ))); 281 }; 282 283 debug!("Register read: {:#x} from {:?}", reg_value, reg); 284 285 Ok(reg_value) 286 } 287 288 fn write_reg(&mut self, reg: Register, val: u64) -> Result<(), PlatformError> { 289 debug!("Register write: {:#x} to {:?}", val, reg); 290 291 // SDM Vol 1 - 3.4.1.1 292 // 293 // 8-bit and 16-bit operands generate an 8-bit or 16-bit result. 294 // The upper 56 bits or 48 bits (respectively) of the destination 295 // general-purpose register are not modified by the operation. 296 let (reg_value, mask): (u64, u64) = if reg.is_gpr64() || reg.is_cr() { 297 (val, !REGISTER_MASK_64) 298 } else if reg.is_gpr32() { 299 (val & REGISTER_MASK_32, !REGISTER_MASK_64) 300 } else if reg.is_gpr16() { 301 (val & REGISTER_MASK_16, !REGISTER_MASK_16) 302 } else if reg.is_gpr8() { 303 if reg == Register::AH 304 || reg == Register::BH 305 || reg == Register::CH 306 || reg == Register::DH 307 { 308 ((val & REGISTER_MASK_8) << 8, !(REGISTER_MASK_8 << 8)) 309 } else { 310 (val & REGISTER_MASK_8, !REGISTER_MASK_8) 311 } 312 } else { 313 return Err(PlatformError::InvalidRegister(anyhow!( 314 "write_reg invalid register {:?}", 315 reg 316 ))); 317 }; 318 319 match reg { 320 Register::RAX | Register::EAX | Register::AX | Register::AL | Register::AH => { 321 set_reg!(self.regs.rax, mask, reg_value); 322 } 323 Register::RBX | Register::EBX | Register::BX | Register::BL | Register::BH => { 324 set_reg!(self.regs.rbx, mask, reg_value); 325 } 326 Register::RCX | Register::ECX | Register::CX | Register::CL | Register::CH => { 327 set_reg!(self.regs.rcx, mask, reg_value); 328 } 329 Register::RDX | Register::EDX | Register::DX | Register::DL | Register::DH => { 330 set_reg!(self.regs.rdx, mask, reg_value); 331 } 332 Register::RSP | Register::ESP | Register::SP => { 333 set_reg!(self.regs.rsp, mask, reg_value) 334 } 335 Register::RBP | Register::EBP | Register::BP => { 336 set_reg!(self.regs.rbp, mask, reg_value) 337 } 338 Register::RSI | Register::ESI | Register::SI | Register::SIL => { 339 set_reg!(self.regs.rsi, mask, reg_value) 340 } 341 Register::RDI | Register::EDI | Register::DI | Register::DIL => { 342 set_reg!(self.regs.rdi, mask, reg_value) 343 } 344 Register::R8 | Register::R8D | Register::R8W | Register::R8L => { 345 set_reg!(self.regs.r8, mask, reg_value) 346 } 347 Register::R9 | Register::R9D | Register::R9W | Register::R9L => { 348 set_reg!(self.regs.r9, mask, reg_value) 349 } 350 Register::R10 | Register::R10D | Register::R10W | Register::R10L => { 351 set_reg!(self.regs.r10, mask, reg_value) 352 } 353 Register::R11 | Register::R11D | Register::R11W | Register::R11L => { 354 set_reg!(self.regs.r11, mask, reg_value) 355 } 356 Register::R12 | Register::R12D | Register::R12W | Register::R12L => { 357 set_reg!(self.regs.r12, mask, reg_value) 358 } 359 Register::R13 | Register::R13D | Register::R13W | Register::R13L => { 360 set_reg!(self.regs.r13, mask, reg_value) 361 } 362 Register::R14 | Register::R14D | Register::R14W | Register::R14L => { 363 set_reg!(self.regs.r14, mask, reg_value) 364 } 365 Register::R15 | Register::R15D | Register::R15W | Register::R15L => { 366 set_reg!(self.regs.r15, mask, reg_value) 367 } 368 Register::CR0 => set_reg!(self.sregs.cr0, mask, reg_value), 369 Register::CR2 => set_reg!(self.sregs.cr2, mask, reg_value), 370 Register::CR3 => set_reg!(self.sregs.cr3, mask, reg_value), 371 Register::CR4 => set_reg!(self.sregs.cr4, mask, reg_value), 372 Register::CR8 => set_reg!(self.sregs.cr8, mask, reg_value), 373 _ => { 374 return Err(PlatformError::InvalidRegister(anyhow!( 375 "write_reg invalid register {:?}", 376 reg 377 ))) 378 } 379 } 380 381 Ok(()) 382 } 383 384 fn read_segment(&self, reg: Register) -> Result<SegmentRegister, PlatformError> { 385 if !reg.is_segment_register() { 386 return Err(PlatformError::InvalidRegister(anyhow!( 387 "read_segment {:?} is not a segment register", 388 reg 389 ))); 390 } 391 392 match reg { 393 Register::CS => Ok(self.sregs.cs), 394 Register::DS => Ok(self.sregs.ds), 395 Register::ES => Ok(self.sregs.es), 396 Register::FS => Ok(self.sregs.fs), 397 Register::GS => Ok(self.sregs.gs), 398 Register::SS => Ok(self.sregs.ss), 399 r => Err(PlatformError::InvalidRegister(anyhow!( 400 "read_segment invalid register {:?}", 401 r 402 ))), 403 } 404 } 405 406 fn write_segment( 407 &mut self, 408 reg: Register, 409 segment_register: SegmentRegister, 410 ) -> Result<(), PlatformError> { 411 if !reg.is_segment_register() { 412 return Err(PlatformError::InvalidRegister(anyhow!("{:?}", reg))); 413 } 414 415 match reg { 416 Register::CS => self.sregs.cs = segment_register, 417 Register::DS => self.sregs.ds = segment_register, 418 Register::ES => self.sregs.es = segment_register, 419 Register::FS => self.sregs.fs = segment_register, 420 Register::GS => self.sregs.gs = segment_register, 421 Register::SS => self.sregs.ss = segment_register, 422 r => return Err(PlatformError::InvalidRegister(anyhow!("{:?}", r))), 423 } 424 425 Ok(()) 426 } 427 428 fn ip(&self) -> u64 { 429 self.regs.rip 430 } 431 432 fn set_ip(&mut self, ip: u64) { 433 self.regs.rip = ip; 434 } 435 436 fn efer(&self) -> u64 { 437 self.sregs.efer 438 } 439 440 fn set_efer(&mut self, efer: u64) { 441 self.sregs.efer = efer 442 } 443 444 fn flags(&self) -> u64 { 445 self.regs.rflags 446 } 447 448 fn set_flags(&mut self, flags: u64) { 449 self.regs.rflags = flags; 450 } 451 452 fn mode(&self) -> Result<CpuMode, PlatformError> { 453 let efer = self.efer(); 454 let cr0 = self.read_reg(Register::CR0)?; 455 let mut mode = CpuMode::Real; 456 457 if (cr0 & CR0_PE) == CR0_PE { 458 mode = CpuMode::Protected; 459 } 460 461 if (efer & EFER_LMA) == EFER_LMA { 462 if mode != CpuMode::Protected { 463 return Err(PlatformError::InvalidState(anyhow!( 464 "Protection must be enabled in long mode" 465 ))); 466 } 467 468 mode = CpuMode::Long; 469 } 470 471 Ok(mode) 472 } 473 } 474 475 pub struct Emulator<'a, T: CpuStateManager> { 476 platform: &'a mut dyn PlatformEmulator<CpuState = T>, 477 insn_map: InstructionMap<T>, 478 } 479 480 impl<'a, T: CpuStateManager> Emulator<'a, T> { 481 pub fn new(platform: &mut dyn PlatformEmulator<CpuState = T>) -> Emulator<T> { 482 let mut insn_map = InstructionMap::<T>::new(); 483 484 // MOV 485 insn_add!(insn_map, mov, Mov_r8_imm8); 486 insn_add!(insn_map, mov, Mov_r8_rm8); 487 insn_add!(insn_map, mov, Mov_r16_imm16); 488 insn_add!(insn_map, mov, Mov_r16_rm16); 489 insn_add!(insn_map, mov, Mov_r32_imm32); 490 insn_add!(insn_map, mov, Mov_r32_rm32); 491 insn_add!(insn_map, mov, Mov_r64_imm64); 492 insn_add!(insn_map, mov, Mov_r64_rm64); 493 insn_add!(insn_map, mov, Mov_rm8_imm8); 494 insn_add!(insn_map, mov, Mov_rm8_r8); 495 insn_add!(insn_map, mov, Mov_rm16_imm16); 496 insn_add!(insn_map, mov, Mov_rm16_r16); 497 insn_add!(insn_map, mov, Mov_rm32_imm32); 498 insn_add!(insn_map, mov, Mov_rm32_r32); 499 insn_add!(insn_map, mov, Mov_rm64_imm32); 500 insn_add!(insn_map, mov, Mov_rm64_r64); 501 502 Emulator { platform, insn_map } 503 } 504 505 fn emulate_insn_stream( 506 &mut self, 507 cpu_id: usize, 508 insn_stream: &[u8], 509 num_insn: Option<usize>, 510 ) -> EmulationResult<T, Exception> { 511 let mut state = self 512 .platform 513 .cpu_state(cpu_id) 514 .map_err(EmulationError::PlatformEmulationError)?; 515 let mut decoder = Decoder::new(64, insn_stream, DecoderOptions::NONE); 516 let mut insn = Instruction::default(); 517 let mut num_insn_emulated: usize = 0; 518 let mut fetched_insn_stream: [u8; 16] = [0; 16]; 519 let mut last_decoded_ip: u64 = state.ip(); 520 let mut stop_emulation: bool = false; 521 522 decoder.set_ip(state.ip()); 523 524 while decoder.can_decode() && !stop_emulation { 525 decoder.decode_out(&mut insn); 526 527 if decoder.last_error() == DecoderError::NoMoreBytes { 528 // The decoder is missing some bytes to decode the current 529 // instruction, for example because the instruction stream 530 // crosses a page boundary. 531 // We fetch 16 more bytes from the instruction segment, 532 // decode and emulate the failing instruction and terminate 533 // the emulation loop. 534 debug!( 535 "Fetching {} bytes from {:#x}", 536 fetched_insn_stream.len(), 537 last_decoded_ip 538 ); 539 540 // fetched_insn_stream is 16 bytes long, enough to contain 541 // any complete x86 instruction. 542 self.platform 543 .fetch(last_decoded_ip, &mut fetched_insn_stream) 544 .map_err(EmulationError::PlatformEmulationError)?; 545 546 debug!("Fetched {:x?}", fetched_insn_stream); 547 548 // Once we have the new stream, we must create a new decoder 549 // and emulate one last instruction from the last decoded IP. 550 decoder = Decoder::new(64, &fetched_insn_stream, DecoderOptions::NONE); 551 decoder.decode_out(&mut insn); 552 if decoder.last_error() != DecoderError::None { 553 return Err(EmulationError::InstructionFetchingError(anyhow!( 554 "{:#x?}", insn 555 ))); 556 } 557 558 stop_emulation = true; 559 } 560 561 // Emulate the decoded instruction 562 self.insn_map 563 .instructions 564 .get(&insn.code()) 565 .ok_or_else(|| { 566 EmulationError::UnsupportedInstruction(anyhow!("{:?}", insn.mnemonic())) 567 })? 568 .emulate(&insn, &mut state, self.platform)?; 569 570 last_decoded_ip = decoder.ip(); 571 num_insn_emulated += 1; 572 573 if let Some(num_insn) = num_insn { 574 if num_insn_emulated >= num_insn { 575 // Exit the decoding loop, do not decode the next instruction. 576 stop_emulation = true; 577 } 578 } 579 } 580 581 state.set_ip(decoder.ip()); 582 Ok(state) 583 } 584 585 /// Emulate all instructions from the instructions stream. 586 pub fn emulate(&mut self, cpu_id: usize, insn_stream: &[u8]) -> EmulationResult<T, Exception> { 587 self.emulate_insn_stream(cpu_id, insn_stream, None) 588 } 589 590 /// Only emulate the first instruction from the stream. 591 /// 592 /// This is useful for cases where we get readahead instruction stream 593 /// but implicitly must only emulate the first instruction, and then return 594 /// to the guest. 595 pub fn emulate_first_insn( 596 &mut self, 597 cpu_id: usize, 598 insn_stream: &[u8], 599 ) -> EmulationResult<T, Exception> { 600 self.emulate_insn_stream(cpu_id, insn_stream, Some(1)) 601 } 602 } 603 604 #[cfg(test)] 605 mod mock_vmm { 606 #![allow(unused_mut)] 607 608 extern crate env_logger; 609 610 use super::*; 611 use crate::arch::emulator::{EmulationError, PlatformEmulator}; 612 use crate::arch::x86::emulator::{Emulator, EmulatorCpuState as CpuState}; 613 use crate::arch::x86::gdt::{gdt_entry, segment_from_gdt}; 614 use crate::arch::x86::Exception; 615 use std::collections::HashMap; 616 use std::sync::{Arc, Mutex}; 617 618 #[derive(Debug, Clone)] 619 pub struct MockVMM { 620 memory: Vec<u8>, 621 state: Arc<Mutex<CpuState>>, 622 } 623 624 unsafe impl Sync for MockVMM {} 625 626 pub type MockResult = Result<(), EmulationError<Exception>>; 627 628 impl MockVMM { 629 pub fn new(ip: u64, regs: HashMap<Register, u64>, memory: Option<(u64, &[u8])>) -> MockVMM { 630 let _ = env_logger::try_init(); 631 let cs_reg = segment_from_gdt(gdt_entry(0xc09b, 0, 0xffffffff), 1); 632 let ds_reg = segment_from_gdt(gdt_entry(0xc093, 0, 0xffffffff), 2); 633 let mut initial_state = CpuState::default(); 634 initial_state.set_ip(ip); 635 initial_state.write_segment(Register::CS, cs_reg).unwrap(); 636 initial_state.write_segment(Register::DS, ds_reg).unwrap(); 637 for (reg, value) in regs { 638 initial_state.write_reg(reg, value).unwrap(); 639 } 640 641 let mut vmm = MockVMM { 642 memory: vec![0; 8192], 643 state: Arc::new(Mutex::new(initial_state)), 644 }; 645 646 if let Some(mem) = memory { 647 vmm.write_memory(mem.0, &mem.1).unwrap(); 648 } 649 650 vmm 651 } 652 653 pub fn emulate_insn(&mut self, cpu_id: usize, insn: &[u8], num_insn: Option<usize>) { 654 let ip = self.cpu_state(cpu_id).unwrap().ip(); 655 let mut emulator = Emulator::new(self); 656 657 let new_state = emulator 658 .emulate_insn_stream(cpu_id, &insn, num_insn) 659 .unwrap(); 660 if num_insn.is_none() { 661 assert_eq!(ip + insn.len() as u64, new_state.ip()); 662 } 663 664 self.set_cpu_state(cpu_id, new_state).unwrap(); 665 } 666 667 pub fn emulate_first_insn(&mut self, cpu_id: usize, insn: &[u8]) { 668 self.emulate_insn(cpu_id, insn, None) 669 } 670 } 671 672 impl PlatformEmulator for MockVMM { 673 type CpuState = CpuState; 674 675 fn read_memory(&self, gva: u64, data: &mut [u8]) -> Result<(), PlatformError> { 676 debug!( 677 "Memory read {} bytes from [{:#x} -> {:#x}]", 678 data.len(), 679 gva, 680 gva 681 ); 682 data.copy_from_slice(&self.memory[gva as usize..gva as usize + data.len()]); 683 Ok(()) 684 } 685 686 fn write_memory(&mut self, gva: u64, data: &[u8]) -> Result<(), PlatformError> { 687 debug!( 688 "Memory write {} bytes at [{:#x} -> {:#x}]", 689 data.len(), 690 gva, 691 gva 692 ); 693 self.memory[gva as usize..gva as usize + data.len()].copy_from_slice(data); 694 695 Ok(()) 696 } 697 698 fn cpu_state(&self, _cpu_id: usize) -> Result<CpuState, PlatformError> { 699 Ok(self.state.lock().unwrap().clone()) 700 } 701 702 fn set_cpu_state( 703 &self, 704 _cpu_id: usize, 705 state: Self::CpuState, 706 ) -> Result<(), PlatformError> { 707 *self.state.lock().unwrap() = state; 708 Ok(()) 709 } 710 711 fn gva_to_gpa(&self, gva: u64) -> Result<u64, PlatformError> { 712 Ok(gva) 713 } 714 715 fn fetch(&self, ip: u64, instruction_bytes: &mut [u8]) -> Result<(), PlatformError> { 716 let rip = self 717 .state 718 .lock() 719 .unwrap() 720 .linearize(Register::CS, ip, false)?; 721 self.read_memory(rip, instruction_bytes) 722 } 723 } 724 } 725 726 #[cfg(test)] 727 mod tests { 728 #![allow(unused_mut)] 729 use super::*; 730 use crate::arch::x86::emulator::mock_vmm::*; 731 732 macro_rules! hashmap { 733 ($( $key: expr => $val: expr ),*) => {{ 734 let mut map = ::std::collections::HashMap::new(); 735 $( map.insert($key, $val); )* 736 map 737 }} 738 } 739 740 #[test] 741 // Emulate truncated instruction stream, which should cause a fetch. 742 // 743 // mov rax, 0x1000 744 // Test with a first instruction truncated. 745 fn test_fetch_first_instruction() -> MockResult { 746 let ip: u64 = 0x1000; 747 let cpu_id = 0; 748 let memory = [ 749 // Code at IP 750 0x48, 0xc7, 0xc0, 0x00, 0x10, 0x00, 0x00, // mov rax, 0x1000 751 0x48, 0x8b, 0x58, 0x10, // mov rbx, qword ptr [rax+10h] 752 // Padding 753 0x00, 0x00, 0x00, 0x00, 0x00, // Padding is all zeroes 754 // Data at IP + 0x10 (0x1234567812345678 in LE) 755 0x78, 0x56, 0x34, 0x12, 0x78, 0x56, 0x34, 0x12, 756 ]; 757 let insn = [ 758 // First instruction is truncated 759 0x48, 0xc7, 0xc0, 0x00, // mov rax, 0x1000 -- Missing bytes: 0x00, 0x10, 0x00, 0x00, 760 ]; 761 762 let mut vmm = MockVMM::new(ip, hashmap![], Some((ip, &memory))); 763 vmm.emulate_insn(cpu_id, &insn, Some(2)); 764 765 let rax: u64 = vmm 766 .cpu_state(cpu_id) 767 .unwrap() 768 .read_reg(Register::RAX) 769 .unwrap(); 770 assert_eq!(rax, ip); 771 772 Ok(()) 773 } 774 775 #[test] 776 // Emulate truncated instruction stream, which should cause a fetch. 777 // 778 // mov rax, 0x1000 779 // mov rbx, qword ptr [rax+10h] 780 // Test with a 2nd instruction truncated. 781 fn test_fetch_second_instruction() -> MockResult { 782 let target_rax: u64 = 0x1234567812345678; 783 let ip: u64 = 0x1000; 784 let cpu_id = 0; 785 let memory = [ 786 // Code at IP 787 0x48, 0xc7, 0xc0, 0x00, 0x10, 0x00, 0x00, // mov rax, 0x1000 788 0x48, 0x8b, 0x58, 0x10, // mov rbx, qword ptr [rax+10h] 789 // Padding 790 0x00, 0x00, 0x00, 0x00, 0x00, // Padding is all zeroes 791 // Data at IP + 0x10 (0x1234567812345678 in LE) 792 0x78, 0x56, 0x34, 0x12, 0x78, 0x56, 0x34, 0x12, 793 ]; 794 let insn = [ 795 0x48, 0xc7, 0xc0, 0x00, 0x10, 0x00, 0x00, // mov rax, 0x1000 796 0x48, 0x8b, // Truncated mov rbx, qword ptr [rax+10h] -- missing [0x58, 0x10] 797 ]; 798 799 let mut vmm = MockVMM::new(ip, hashmap![], Some((ip, &memory))); 800 vmm.emulate_insn(cpu_id, &insn, Some(2)); 801 802 let rbx: u64 = vmm 803 .cpu_state(cpu_id) 804 .unwrap() 805 .read_reg(Register::RBX) 806 .unwrap(); 807 assert_eq!(rbx, target_rax); 808 809 Ok(()) 810 } 811 } 812