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Searched refs:phase (Results 1 – 25 of 251) sorted by relevance

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/src/sys/contrib/zstd/lib/compress/
H A Dzstd_cwksp.h156 ZSTD_cwksp_alloc_phase_e phase; member
280 ZSTD_cwksp_internal_advance_phase(ZSTD_cwksp* ws, ZSTD_cwksp_alloc_phase_e phase) in ZSTD_cwksp_internal_advance_phase() argument
282 assert(phase >= ws->phase); in ZSTD_cwksp_internal_advance_phase()
283 if (phase > ws->phase) { in ZSTD_cwksp_internal_advance_phase()
285 if (ws->phase < ZSTD_cwksp_alloc_buffers && in ZSTD_cwksp_internal_advance_phase()
286 phase >= ZSTD_cwksp_alloc_buffers) { in ZSTD_cwksp_internal_advance_phase()
291 if (ws->phase < ZSTD_cwksp_alloc_aligned && in ZSTD_cwksp_internal_advance_phase()
292 phase >= ZSTD_cwksp_alloc_aligned) { in ZSTD_cwksp_internal_advance_phase()
313 ws->phase = phase; in ZSTD_cwksp_internal_advance_phase()
331 ZSTD_cwksp_reserve_internal(ZSTD_cwksp* ws, size_t bytes, ZSTD_cwksp_alloc_phase_e phase) in ZSTD_cwksp_reserve_internal() argument
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/src/sys/contrib/openzfs/module/zstd/lib/compress/
H A Dzstd_cwksp.h168 ZSTD_cwksp_alloc_phase_e phase; member
320 ZSTD_cwksp_internal_advance_phase(ZSTD_cwksp* ws, ZSTD_cwksp_alloc_phase_e phase) in ZSTD_cwksp_internal_advance_phase() argument
322 assert(phase >= ws->phase); in ZSTD_cwksp_internal_advance_phase()
323 if (phase > ws->phase) { in ZSTD_cwksp_internal_advance_phase()
325 if (ws->phase < ZSTD_cwksp_alloc_aligned_init_once && in ZSTD_cwksp_internal_advance_phase()
326 phase >= ZSTD_cwksp_alloc_aligned_init_once) { in ZSTD_cwksp_internal_advance_phase()
344 ws->phase = phase; in ZSTD_cwksp_internal_advance_phase()
362 ZSTD_cwksp_reserve_internal(ZSTD_cwksp* ws, size_t bytes, ZSTD_cwksp_alloc_phase_e phase) in ZSTD_cwksp_reserve_internal() argument
365 if (ZSTD_isError(ZSTD_cwksp_internal_advance_phase(ws, phase)) || bytes == 0) { in ZSTD_cwksp_reserve_internal()
449 const ZSTD_cwksp_alloc_phase_e phase = ZSTD_cwksp_alloc_aligned_init_once; in ZSTD_cwksp_reserve_table() local
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/src/contrib/ntp/libparse/
H A Dclk_meinberg.c225 unsigned short phase; /* current input phase */ member
610 if ( msg_buf->phase == MBG_NONE ) in gps_input()
618 msg_buf->phase = MBG_HEADER; /* receiving header */ in gps_input()
625 msg_buf->phase = MBG_STRING; /* prepare to receive ASCII ETX delimited message */ in gps_input()
643 if ((msg_buf->phase == MBG_STRING) && in gps_input()
651 msg_buf->phase = MBG_NONE; /* buffer overflow - discard */ in gps_input()
658 switch (msg_buf->phase) in gps_input()
667 …parseprintf(DD_PARSE, ("gps_input: %s complete\n", (msg_buf->phase == MBG_DATA) ? "data" : "header… in gps_input()
674 msg_buf->phase = MBG_NONE; in gps_input()
690 if ( msg_buf->phase == MBG_HEADER ) in gps_input()
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/src/sys/kern/
H A Dkern_poll.c238 static uint32_t phase; variable
239 SYSCTL_UINT(_kern_polling, OID_AUTO, phase, CTLFLAG_RD,
240 &phase, 0, "Polling phase");
316 phase = 0; in hardclock_device_poll()
319 if (phase <= 2) { in hardclock_device_poll()
320 if (phase != 0) in hardclock_device_poll()
322 phase = 1; in hardclock_device_poll()
326 phase = 2; in hardclock_device_poll()
387 phase = 5; in netisr_pollmore()
411 phase = 0; in netisr_pollmore()
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/src/crypto/openssl/crypto/
H A Dself_test_core.c23 const char *phase; member
81 (char *)st->phase, 0); in self_test_setparams()
99 ret->phase = ""; in OSSL_SELF_TEST_new()
116 st->phase = OSSL_SELF_TEST_PHASE_START; in OSSL_SELF_TEST_onbegin()
131 st->phase = (ret == 1 ? OSSL_SELF_TEST_PHASE_PASS : OSSL_SELF_TEST_PHASE_FAIL); in OSSL_SELF_TEST_onend()
135 st->phase = OSSL_SELF_TEST_PHASE_NONE; in OSSL_SELF_TEST_onend()
152 st->phase = OSSL_SELF_TEST_PHASE_CORRUPT; in OSSL_SELF_TEST_oncorrupt_byte()
/src/sys/contrib/device-tree/Bindings/mmc/
H A Dexynos-dw-mshc.txt32 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
33 in transmit mode and CIU clock phase shift value in receive mode for single
37 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
38 in transmit mode and CIU clock phase shift value in receive mode for double
41 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
47 - First Cell: CIU clock phase shift value for tx mode.
48 - Second Cell: CIU clock phase shift value for rx mode.
51 - valid value for tx phase shift and rx phase shift is 0 to 7.
52 - when CIU clock divider value is set to 3, all possible 8 phase shift
55 phase shift clocks should be 0.
/src/sys/contrib/openzfs/tests/zfs-tests/cmd/
H A Dsuid_write_to_file.c38 const char *name, *phase; in main() local
77 phase = argv[2]; in main()
78 if (strcmp(phase, "PRECRASH") == 0) { in main()
114 } else if (strcmp(phase, "REPLAY") == 0) { in main()
117 fprintf(stderr, "Invalid phase %s\n", phase); in main()
H A Dxattrtest.c94 static int phase = PHASE_ALL; variable
189 phase = strtol(optarg, NULL, 0); in parse_args()
190 if (phase <= PHASE_ALL || phase >= PHASE_INVAL) { in parse_args()
223 fprintf(stdout, "only: %d\n", phase); in parse_args()
293 post_hook(const char *phase) in post_hook() argument
295 char *argv[3] = { (char *)script, (char *)phase, NULL }; in post_hook()
690 if (phase == PHASE_ALL || phase == PHASE_CREATE) { in main()
696 if (phase == PHASE_ALL || phase == PHASE_SETXATTR) { in main()
702 if (phase == PHASE_ALL || phase == PHASE_GETXATTR) { in main()
708 if (!keep_files && (phase == PHASE_ALL || phase == PHASE_UNLINK)) { in main()
/src/contrib/tcpdump/
H A Dprint-isakmp.c565 uint32_t phase,\
603 uint32_t phase,
616 const u_char *ep, uint32_t phase,
666 uint32_t phase,
993 const u_char *ep, uint32_t phase, uint32_t doi0 _U_, in ikev1_sa_print() argument
1037 cp = ikev1_sub_print(ndo, ISAKMP_NPTYPE_P, ext, ep, phase, doi, proto0, in ikev1_sa_print()
1049 const u_char *ep, uint32_t phase, uint32_t doi0, in ikev1_p_print() argument
1073 cp = ikev1_sub_print(ndo, ISAKMP_NPTYPE_T, ext, ep, phase, doi0, in ikev1_p_print()
1213 const u_char *ep, uint32_t phase _U_, uint32_t doi _U_, in ikev1_t_print()
1281 const u_char *ep _U_, uint32_t phase _U_, uint32_t doi _U_, in ikev1_ke_print()
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/src/crypto/openssl/test/
H A Dprovider_status_test.c54 const char *phase = NULL, *type = NULL, *desc = NULL; in self_test_events() local
64 phase = (const char *)p->data; in self_test_events()
76 if (strcmp(phase, OSSL_SELF_TEST_PHASE_START) == 0) in self_test_events()
78 else if (strcmp(phase, OSSL_SELF_TEST_PHASE_PASS) == 0 in self_test_events()
79 || strcmp(phase, OSSL_SELF_TEST_PHASE_FAIL) == 0) in self_test_events()
80 BIO_printf(bio_out, "%s\n", phase); in self_test_events()
85 if (corrupt && strcmp(phase, OSSL_SELF_TEST_PHASE_CORRUPT) == 0) in self_test_events()
/src/sys/contrib/openzfs/include/os/freebsd/spl/sys/
H A Dsysmacros.h233 #define P2PHASEUP(x, align, phase) ((phase) - (((phase) - (x)) & -(align))) argument
272 #define P2PHASEUP_TYPED(x, align, phase, type) \ argument
273 ((type)(phase) - (((type)(phase) - (type)(x)) & -(type)(align)))
/src/contrib/wpa/hostapd/
H A Dhostapd.eap_user12 # [2] flag in the end of the line can be used to mark users for tunneled phase
14 # identity can be used in the unencrypted phase 1 and the real user identity
15 # is transmitted only within the encrypted tunnel in phase 2. If non-anonymous
16 # access is needed, two user entries is needed, one for phase 1 and another
17 # with the same username for phase 2.
26 # this are to set anonymous phase 1 identity for EAP-PEAP and EAP-TTLS and to
28 # first matching entry is selected, so * should be used as the last phase 1
34 # is only allowed for phase 1 identities.
94 # Default to EAP-SIM and EAP-AKA based on fixed identity prefixes in phase 2
/src/sys/contrib/device-tree/Bindings/mfd/
H A Daxp20x.txt127 DCDC2 : DC-DC buck : vin2-supply : poly-phase capable
128 DCDC3 : DC-DC buck : vin3-supply : poly-phase capable
130 DCDC5 : DC-DC buck : vin5-supply : poly-phase capable
131 DCDC6 : DC-DC buck : vin6-supply : poly-phase capable
154 DCDCA : DC-DC buck : vina-supply : poly-phase capable
155 DCDCB : DC-DC buck : vinb-supply : poly-phase capable
156 DCDCC : DC-DC buck : vinc-supply : poly-phase capable
157 DCDCD : DC-DC buck : vind-supply : poly-phase capable
158 DCDCE : DC-DC buck : vine-supply : poly-phase capable
171 Additionally, the AXP806 DC-DC regulators support poly-phase arrangements
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/src/contrib/libxo/xolint/
H A Dxolint.pl246 my $phase = 0;
269 $phase = 0;
271 } elsif ($phase == 0 && $ch eq ":") {
272 $phase += 1;
275 $phase += 1;
290 $build[$phase] .= $ch;
/src/sys/contrib/device-tree/Bindings/sound/
H A Dmax98504.txt20 applied during the "attack hold" and "timed hold" phase, the value must be
22 - maxim,brownout-attack-hold-ms - the brownout attack hold phase time in ms,
24 - maxim,brownout-timed-hold-ms - the brownout timed hold phase time in ms,
26 - maxim,brownout-release-rate-ms - the brownout release phase step time in ms,
/src/sys/contrib/device-tree/Bindings/leds/backlight/
H A Dsky81452-backlight.txt14 - skyworks,phase-shift : Enable phase shift mode
27 skyworks,phase-shift;
/src/crypto/krb5/src/windows/installer/wix/custom/
H A Dcustom.cpp152 DWORD phase = 0;
169 phase = 1;
175 phase = 2;
181 phase = 3;
191 phase = 4;
198 phase = 5;
204 phase = 6;
210 phase = 7;
216 phase = 8;
223 phase = 9;
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/src/tests/sys/cddl/zfs/tests/txg_integrity/
H A Dtxg_integrity.c310 static phase_t phase; variable
429 if (perm_idx == NUM_CHUNKS / 2 && phase == follower_syncs){ in follower()
458 if (perm_idx == NUM_CHUNKS / 2 && phase == leader_syncs){ in leader()
495 for(phase=leader_syncs; phase < NUM_PHASES; phase++){ in main()
/src/sys/cddl/contrib/opensolaris/uts/common/sys/
H A Dsysmacros.h287 #define P2PHASEUP(x, align, phase) ((phase) - (((phase) - (x)) & -(align))) argument
326 #define P2PHASEUP_TYPED(x, align, phase, type) \ argument
327 ((type)(phase) - (((type)(phase) - (type)(x)) & -(type)(align)))
/src/sys/contrib/openzfs/lib/libspl/include/sys/
H A Dsysmacros.h108 #define P2PHASEUP_TYPED(x, align, phase, type) \ argument
109 ((type)(phase) - (((type)(phase) - (type)(x)) & -(type)(align)))
/src/sys/contrib/device-tree/Bindings/spi/
H A Dspi-samsung.txt61 - samsung,spi-feedback-delay: The sampling phase shift to be applied on the
65 - 0: No phase shift.
66 - 1: 90 degree phase shift sampling.
67 - 2: 180 degree phase shift sampling.
68 - 3: 270 degree phase shift sampling.
/src/sys/contrib/device-tree/src/arm/intel/ixp/
H A Dintel-ixp42x-gateworks-gw2348.dts89 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
90 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
91 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
92 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
93 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
/src/sys/crypto/openssl/arm/
H A Dghashv8-armx.S48 INST(0x26,0x4e,0xe0,0xf2) @ pmull q10,q0,q11 @ 1st phase
54 vext.8 q10,q0,q0,#8 @ 2nd phase
87 INST(0x26,0x4e,0xe0,0xf2) @ pmull q10,q0,q11 @ 1st phase of reduction
93 vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
180 INST(0x26,0x4e,0xe0,0xf2) @ pmull q10,q0,q11 @ 1st phase of reduction
193 vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
220 INST(0x26,0x4e,0xe0,0xf2) @ pmull q10,q0,q11 @ 1st phase of reduction
226 vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
/src/sys/contrib/device-tree/Bindings/clock/
H A Daltr_socfpga.txt26 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
/src/crypto/openssl/util/
H A Dmkerr.pl32 sub phase subroutine
185 &phase("Reading state");
258 &phase("Scanning source");
290 &phase("Writing files");
658 &phase("Ending");

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