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Searched refs:isCommutable (Results 1 – 25 of 93) sorted by relevance

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/src/contrib/llvm-project/llvm/include/llvm/Target/
H A DGenericOpcodes.td34 let isCommutable = baseInst.isCommutable;
277 let isCommutable = true;
285 let isCommutable = false;
293 let isCommutable = true;
301 let isCommutable = false;
309 let isCommutable = false;
317 let isCommutable = false;
325 let isCommutable = false;
333 let isCommutable = false;
341 let isCommutable = false;
[all …]
/src/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td47 let isCommutable = 1 in
50 let isCommutable = 1 in
59 let isCommutable = 1 in {
62 } // isCommutable = 1
83 let isCommutable = 1 in {
86 } // isCommutable = 1
H A DWebAssemblyInstrInteger.td49 let isCommutable = 1 in
52 let isCommutable = 1 in
61 let isCommutable = 1 in {
65 } // isCommutable = 1
72 let isCommutable = 1 in {
75 } // isCommutable = 1
H A DWebAssemblyInstrSIMD.td751 let isCommutable = 1 in {
755 } // isCommutable = 1
758 let isCommutable = 1 in {
762 } // isCommutable = 1
822 let isCommutable = commutable in
1088 let isCommutable = 1 in {
1092 } // isCommutable = 1
1102 let isCommutable = 1 in
1106 let isCommutable = 1 in {
1111 } // isCommutable = 1
[all …]
/src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h290 bool isCommutable : 1; ///< Is a commutable instruction. variable
320 isCallOp(false), isTwoAddress(false), isCommutable(false), in SUnit()
332 isCallOp(false), isTwoAddress(false), isCommutable(false), in SUnit()
343 isTwoAddress(false), isCommutable(false), hasPhysRegUses(false), in SUnit()
/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td312 let isCommutable = 1;
317 let isCommutable = 1;
322 let isCommutable = 1;
327 let isCommutable = 1;
348 let isCommutable = 1;
357 let isCommutable = 1;
H A DMipsInstrFPU.td117 let isCommutable = IsComm;
142 let isCommutable = IsComm;
289 let isCommutable = 1;
294 let isCommutable = 1;
299 let isCommutable = 1;
304 let isCommutable = 1;
325 let isCommutable = 1;
334 let isCommutable = 1;
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSOPInstructions.td641 let isCommutable = 1 in {
646 } // End isCommutable = 1
654 let isCommutable = 1 in {
657 } // End isCommutable = 1
663 let isCommutable = 1 in {
676 } // End isCommutable = 1
681 let isCommutable = 1;
688 let isCommutable = 1;
709 let isCommutable = 1 in {
757 } // End isCommutable = 1
[all …]
H A DVOP2Instructions.td722 let isCommutable = 1 in {
779 } // End isCommutable = 1
825 let isCommutable = 1 in {
831 } // End isCommutable = 1
933 let isCommutable = 1 in {
947 } // End isCommutable = 1
966 let isCommutable = 1 in {
970 } // End isCommutable = 1
981 let isCommutable = 1 in {
988 } // End isCommutable = 1
[all …]
H A DVOP3Instructions.td126 let isCommutable = 1 in {
198 } // End isCommutable = 1
216 let isCommutable = 1 in {
223 } // End isCommutable = 1
234 let isCommutable = 1 in {
239 } // End isCommutable = 1
321 let isCommutable = 1, SchedRW = [WriteIntMul, WriteSALU], IsInvalidSingleUseConsumer = 1 in {
331 } // End isCommutable = 1, SchedRW = [WriteIntMul, WriteSALU], IsInvalidSingleUseConsumer = 1
347 let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in {
396 } // End SubtargetPredicate = Has16BitInsts, isCommutable = 1
[all …]
/src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrVector.td474 let isCommutable = 1 in {
484 let isCommutable = 1 in {
503 let isCommutable = 1 in
509 let isCommutable = 1 in {
542 let isCommutable = 1 in {
579 let isCommutable = 1 in {
595 let isCommutable = 1 in {
611 let isCommutable = 1 in {
655 let isCommutable = 1 in {
700 let Predicates = [FeatureVectorEnhancements1], isCommutable = 1 in {
[all …]
H A DSystemZInstrHFP.td132 let isCommutable = 1 in {
143 let isCommutable = 1 in {
171 let isCommutable = 1 in {
H A DSystemZRegisterInfo.cpp96 if (Use.isCommutable()) in getRegAllocationHints()
102 Use.isCommutable()) { in getRegAllocationHints()
H A DSystemZInstrDFP.td146 let isCommutable = 1 in {
168 let isCommutable = 1 in {
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DREADME_P9.txt187 . isCommutable = 1
191 . isCommutable = 0
212 . isCommutable = 1
216 . isCommutable = 0
224 . isCommutable = 1
276 . isCommutable = 1
H A DPPCInstrAltivec.td458 let isCommutable = 1 in {
475 } // isCommutable
488 let isCommutable = 1 in {
510 } // isCommutable
512 let isCommutable = 1 in
562 let isCommutable = 1 in {
584 } // isCommutable
620 let isCommutable = 1 in {
637 } // isCommutable
684 let isCommutable = 1 in {
[all …]
H A DPPCInstrDFP.td18 let isCommutable = 1 in {
32 let isCommutable = 1 in {
/src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp98 SU->isCommutable = Old->isCommutable; in Clone()
461 if (MCID.isCommutable()) in AddSchedEdges()
462 SU.isCommutable = true; in AddSchedEdges()
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFMA.td98 let Constraints = "$src1 = $dst", hasSideEffects = 0, isCommutable = 1,
240 let Constraints = "$src1 = $dst", isCommutable = 1, isCodeGenOnly = 1,
267 let Constraints = "$src1 = $dst", isCommutable = 1, hasSideEffects = 0,
393 let isCommutable = 1 in
470 let isCommutable = 1 in
497 let isCommutable = 1 in
H A DX86InstrCMovSetCC.td17 let isCommutable = 1, SchedRW = [WriteCMOV] in
32 let isCommutable = 1, SchedRW = [WriteCMOV] in {
H A DX86CompressEVEX.cpp203 if (!Desc.isCommutable() || Desc.getNumOperands() < 3 || in CompressEVEXImpl()
/src/contrib/llvm-project/llvm/utils/TableGen/
H A DInstrDocsEmitter.cpp129 FLAG(isCommutable) in EmitInstrDocs()
/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoSFB.td14 Constraints = "$dst = $falsev", isCommutable = 1, Size = 8 in {
32 Constraints = "$dst = $falsev", isCommutable = 1, Size = 6 in {
/src/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h481 bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); } in isCommutable() function
/src/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenInstruction.h263 bool isCommutable : 1; variable

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