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Searched refs:getOperandCycle (Results 1 – 7 of 7) sorted by relevance

/src/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h168 std::optional<unsigned> getOperandCycle(unsigned ItinClassIndx, in getOperandCycle() function
214 std::optional<unsigned> DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
215 std::optional<unsigned> UseCycle = getOperandCycle(UseClass, UseIdx); in getOperandLatency()
/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp191 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx); in computeOperandLatency()
H A DTargetInstrInfo.cpp1453 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1524 ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
/src/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp186 if (std::optional<unsigned> OperCycle = IID.getOperandCycle(SCClass, Idx)) in getItineraryLatency()
/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3883 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3923 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
3956 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
3995 return ItinData->getOperandCycle(UseClass, UseIdx); in getSTMUseCycle()
4034 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
4075 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); in getOperandLatency()
4474 ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); in getOperandLatency()
4836 ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
H A DARMISelLowering.cpp1995 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2U) in getSchedulingPreference()
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp158 std::optional<unsigned> Cycle = ItinData->getOperandCycle(DefClass, i); in getInstrLatency()