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Searched refs:addRegisterClass (Results 1 – 25 of 28) sorted by relevance

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/src/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp74 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass() function in __anon854007cb0111::RegisterBank
312 Bank.addRegisterClass(RC); in run()
/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp58 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
59 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
60 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
61 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
62 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
63 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
72 addRegisterClass(MVT::v16i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
73 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
74 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
76 addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
[all …]
H A DHexagonISelLowering.cpp1484 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); in HexagonTargetLowering()
1485 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa in HexagonTargetLowering()
1486 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa in HexagonTargetLowering()
1487 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba in HexagonTargetLowering()
1488 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1489 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1490 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1491 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1492 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1493 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp61 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass); in WebAssemblyTargetLowering()
62 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass); in WebAssemblyTargetLowering()
63 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass); in WebAssemblyTargetLowering()
64 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass); in WebAssemblyTargetLowering()
66 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
67 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
68 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
69 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
70 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
71 addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp88 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
89 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
91 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering()
92 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering()
94 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
99 addRegisterClass(MVT::f64, V64RegClass); in SITargetLowering()
100 addRegisterClass(MVT::v2f32, V64RegClass); in SITargetLowering()
101 addRegisterClass(MVT::Untyped, V64RegClass); in SITargetLowering()
103 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass); in SITargetLowering()
104 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96)); in SITargetLowering()
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H A DR600ISelLowering.cpp33 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
38 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp40 addRegisterClass(MVT::i32, &CSKY::GPRRegClass); in CSKYTargetLowering()
44 addRegisterClass(MVT::f32, &CSKY::sFPR32RegClass); in CSKYTargetLowering()
46 addRegisterClass(MVT::f32, &CSKY::FPR32RegClass); in CSKYTargetLowering()
49 addRegisterClass(MVT::f64, &CSKY::sFPR64RegClass); in CSKYTargetLowering()
51 addRegisterClass(MVT::f64, &CSKY::FPR64RegClass); in CSKYTargetLowering()
/src/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp85 addRegisterClass(MVT::i32, &VE::I32RegClass); in initRegisterClasses()
86 addRegisterClass(MVT::i64, &VE::I64RegClass); in initRegisterClasses()
87 addRegisterClass(MVT::f32, &VE::F32RegClass); in initRegisterClasses()
88 addRegisterClass(MVT::f64, &VE::I64RegClass); in initRegisterClasses()
89 addRegisterClass(MVT::f128, &VE::F128RegClass); in initRegisterClasses()
93 addRegisterClass(VecVT, &VE::V64RegClass); in initRegisterClasses()
94 addRegisterClass(MVT::v256i1, &VE::VMRegClass); in initRegisterClasses()
95 addRegisterClass(MVT::v512i1, &VE::VM512RegClass); in initRegisterClasses()
/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp67 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
70 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()
88 addRegisterClass(VecTy, &Mips::DSPRRegClass); in MipsSETargetLowering()
123 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass); in MipsSETargetLowering()
164 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); in MipsSETargetLowering()
169 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); in MipsSETargetLowering()
171 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering()
316 addRegisterClass(Ty, RC); in addMSAIntType()
370 addRegisterClass(Ty, RC); in addMSAFloatType()
H A DMips16ISelLowering.cpp125 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); in Mips16TargetLowering()
/src/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp58 addRegisterClass(MVT::i64, &BPF::GPRRegClass); in BPFTargetLowering()
60 addRegisterClass(MVT::i32, &BPF::GPR32RegClass); in BPFTargetLowering()
/src/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp479 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass); in NVPTXTargetLowering()
480 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
481 addRegisterClass(MVT::v2i16, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
482 addRegisterClass(MVT::v4i8, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
483 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
484 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass); in NVPTXTargetLowering()
485 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass); in NVPTXTargetLowering()
486 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass); in NVPTXTargetLowering()
487 addRegisterClass(MVT::f16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
488 addRegisterClass(MVT::v2f16, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp93 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass); in SystemZTargetLowering()
95 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass); in SystemZTargetLowering()
96 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass); in SystemZTargetLowering()
99 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass); in SystemZTargetLowering()
100 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass); in SystemZTargetLowering()
102 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass); in SystemZTargetLowering()
103 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass); in SystemZTargetLowering()
106 addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass); in SystemZTargetLowering()
108 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass); in SystemZTargetLowering()
111 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass); in SystemZTargetLowering()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1596 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); in SparcTargetLowering()
1598 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); in SparcTargetLowering()
1599 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); in SparcTargetLowering()
1600 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering()
1603 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); in SparcTargetLowering()
1607 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass); in SparcTargetLowering()
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp183 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
186 addRegisterClass(MVT::f32, &PPC::GPRCRegClass); in PPCTargetLowering()
189 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering()
191 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
192 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
311 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering()
745 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering()
943 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
944 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering()
945 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp387 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); in AArch64TargetLowering()
388 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); in AArch64TargetLowering()
391 addRegisterClass(MVT::i64x8, &AArch64::GPR64x8ClassRegClass); in AArch64TargetLowering()
397 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
398 addRegisterClass(MVT::bf16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
399 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); in AArch64TargetLowering()
400 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); in AArch64TargetLowering()
401 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); in AArch64TargetLowering()
405 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); in AArch64TargetLowering()
406 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp49 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); in MSP430TargetLowering()
50 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); in MSP430TargetLowering()
/src/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp100 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); in ARCTargetLowering()
/src/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp47 addRegisterClass(MVT::i32, &Xtensa::ARRegClass); in XtensaTargetLowering()
/src/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp58 addRegisterClass(MVT::i8, &M68k::DR8RegClass); in M68kTargetLowering()
59 addRegisterClass(MVT::i16, &M68k::XR16RegClass); in M68kTargetLowering()
60 addRegisterClass(MVT::i32, &M68k::XR32RegClass); in M68kTargetLowering()
/src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp53 addRegisterClass(GRLenVT, &LoongArch::GPRRegClass); in LoongArchTargetLowering()
55 addRegisterClass(MVT::f32, &LoongArch::FPR32RegClass); in LoongArchTargetLowering()
57 addRegisterClass(MVT::f64, &LoongArch::FPR64RegClass); in LoongArchTargetLowering()
66 addRegisterClass(VT, &LoongArch::LSX128RegClass); in LoongArchTargetLowering()
70 addRegisterClass(VT, &LoongArch::LASX256RegClass); in LoongArchTargetLowering()
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp196 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
197 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
198 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
200 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
639 addRegisterClass(MVT::f16, Subtarget.hasAVX512() ? &X86::FR16XRegClass in X86TargetLowering()
641 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass in X86TargetLowering()
643 addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass in X86TargetLowering()
723 addRegisterClass(MVT::f32, &X86::FR32RegClass); in X86TargetLowering()
725 addRegisterClass(MVT::f64, &X86::RFP64RegClass); in X86TargetLowering()
755 addRegisterClass(MVT::f64, &X86::RFP64RegClass); in X86TargetLowering()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp40 addRegisterClass(MVT::i8, &AVR::GPR8RegClass); in AVRTargetLowering()
41 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); in AVRTargetLowering()
/src/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp77 addRegisterClass(MVT::i32, &Lanai::GPRRegClass); in LanaiTargetLowering()
/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp121 addRegisterClass(XLenVT, &RISCV::GPRRegClass); in RISCVTargetLowering()
123 addRegisterClass(MVT::i32, &RISCV::GPRRegClass); in RISCVTargetLowering()
126 addRegisterClass(MVT::f16, &RISCV::FPR16RegClass); in RISCVTargetLowering()
128 addRegisterClass(MVT::bf16, &RISCV::FPR16RegClass); in RISCVTargetLowering()
130 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass); in RISCVTargetLowering()
132 addRegisterClass(MVT::f64, &RISCV::FPR64RegClass); in RISCVTargetLowering()
134 addRegisterClass(MVT::f16, &RISCV::GPRF16RegClass); in RISCVTargetLowering()
136 addRegisterClass(MVT::f32, &RISCV::GPRF32RegClass); in RISCVTargetLowering()
139 addRegisterClass(MVT::f64, &RISCV::GPRRegClass); in RISCVTargetLowering()
141 addRegisterClass(MVT::f64, &RISCV::GPRPairRegClass); in RISCVTargetLowering()
[all …]

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