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Searched refs:ZPR (Results 1 – 6 of 6) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SVEInstrInfo.td1273 (!cast<Instruction>(Inst # _SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>;
1276 (!cast<Instruction>(Inst # _SXTW_SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>;
1279 (!cast<Instruction>(Inst # _UXTW_SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>;
1285 (!cast<Instruction>(Inst # _IMM) PPR:$gp, ZPR:$ptrs, ImmTy:$imm)>;
1288 (!cast<Instruction>(Inst) PPR:$gp, GPR64:$base, ZPR:$offs)>;
1291 (!cast<Instruction>(Inst # _SXTW) PPR:$gp, GPR64:$base, ZPR:$offs)>;
1294 (!cast<Instruction>(Inst # _UXTW) PPR:$gp, GPR64:$base, ZPR:$offs)>;
1299 (Inst PPR:$gp, GPR64:$base, ZPR:$offs)>;
1507 (!cast<Instruction>(Inst # _SCALED) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>;
1510 (!cast<Instruction>(Inst # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>;
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H A DAArch64RegisterInfo.td1134 def ZPR : ZPRClass<31> {
1148 # Width # ", AArch64::ZPR"
1163 def ZPRAny : ZPRRegOp<"", ZPRAsmOpAny, ElementSizeNone, ZPR>;
1164 def ZPR8 : ZPRRegOp<"b", ZPRAsmOp8, ElementSizeB, ZPR>;
1165 def ZPR16 : ZPRRegOp<"h", ZPRAsmOp16, ElementSizeH, ZPR>;
1166 def ZPR32 : ZPRRegOp<"s", ZPRAsmOp32, ElementSizeS, ZPR>;
1167 def ZPR64 : ZPRRegOp<"d", ZPRAsmOp64, ElementSizeD, ZPR>;
1168 def ZPR128 : ZPRRegOp<"q", ZPRAsmOp128, ElementSizeQ, ZPR>;
1194 class FPRasZPROperand<int Width> : RegisterOperand<ZPR> {
1213 def ZSeqPairs : RegisterTuples<[zsub0, zsub1], [(rotl ZPR, 0), (rotl ZPR, 1)]>;
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H A DAArch64RegisterBanks.td16 def FPRRegBank : RegisterBank<"FPR", [QQQQ, ZPR]>;
H A DSVEInstrFormats.td597 : Pat<(vt (op (pt PPR_3b:$Pg), (vt ZPR:$Zs1), (vt (splat_vector (it immL))))),
1380 …def : Pat<(nxv16i8 (splat_vector (i32 (vector_extract (nxv16i8 ZPR:$vec), sve_elm_idx_extdup_b:$in…
1381 (!cast<Instruction>(NAME # _B) ZPR:$vec, sve_elm_idx_extdup_b:$index)>;
1382 …def : Pat<(nxv8i16 (splat_vector (i32 (vector_extract (nxv8i16 ZPR:$vec), sve_elm_idx_extdup_h:$in…
1383 (!cast<Instruction>(NAME # _H) ZPR:$vec, sve_elm_idx_extdup_h:$index)>;
1384 …def : Pat<(nxv4i32 (splat_vector (i32 (vector_extract (nxv4i32 ZPR:$vec), sve_elm_idx_extdup_s:$in…
1385 (!cast<Instruction>(NAME # _S) ZPR:$vec, sve_elm_idx_extdup_s:$index)>;
1386 …def : Pat<(nxv2i64 (splat_vector (i64 (vector_extract (nxv2i64 ZPR:$vec), sve_elm_idx_extdup_d:$in…
1387 (!cast<Instruction>(NAME # _D) ZPR:$vec, sve_elm_idx_extdup_d:$index)>;
1388 …def : Pat<(nxv8f16 (splat_vector (f16 (vector_extract (nxv8f16 ZPR:$vec), sve_elm_idx_extdup_h:$in…
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H A DAArch64FrameLowering.cpp2917 enum RegType { GPR, FPR64, FPR128, PPR, ZPR, VG } Type; enumerator
2931 case ZPR: in getScale()
2938 bool isScalable() const { return Type == PPR || Type == ZPR; } in isScalable()
2993 RPI.Type = RegPairInfo::ZPR; in computeCalleeSaveRegisterPairs()
3032 case RegPairInfo::ZPR: in computeCalleeSaveRegisterPairs()
3217 case RegPairInfo::ZPR: in spillCalleeSavedRegisters()
3322 return c.Type == RegPairInfo::ZPR; in spillCalleeSavedRegisters()
3377 if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) { in spillCalleeSavedRegisters()
3421 auto IsZPR = [](const RegPairInfo &c) { return c.Type == RegPairInfo::ZPR; }; in restoreCalleeSavedRegisters()
3458 case RegPairInfo::ZPR: in restoreCalleeSavedRegisters()
/src/sys/contrib/device-tree/Bindings/mmc/
H A Dmarvell,xenon-sdhci.txt66 Set PHY ZPR value.
69 ZPR is set as 0xF by default if this property is not provided.