| /src/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | exynos7-clk.h | 98 #define SCLK_UART3 6 macro
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| H A D | s5pv210.h | 194 #define SCLK_UART3 172 macro
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| H A D | rk3188-cru-common.h | 23 #define SCLK_UART3 67 macro
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| H A D | rk3308-cru.h | 24 #define SCLK_UART3 20 macro
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| H A D | rk3368-cru.h | 33 #define SCLK_UART3 80 macro
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| H A D | rk3288-cru.h | 35 #define SCLK_UART3 80 macro
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| H A D | rockchip,rk3562-cru.h | 198 #define SCLK_UART3 186 macro
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| H A D | px30-cru.h | 28 #define SCLK_UART3 26 macro
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| H A D | rockchip,rk3528-cru.h | 40 #define SCLK_UART3 28 macro
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| H A D | rockchip,rv1126-cru.h | 90 #define SCLK_UART3 24 macro
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| H A D | rockchip,rk3576-cru.h | 160 #define SCLK_UART3 142 macro
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| H A D | rk3399-cru.h | 41 #define SCLK_UART3 84 macro
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| H A D | rockchip,rk3588-cru.h | 194 #define SCLK_UART3 179 macro
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| H A D | rk3568-cru.h | 359 #define SCLK_UART3 295 macro
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| /src/sys/dev/clk/rockchip/ |
| H A D | rk3399_cru_dt.h | 32 #define SCLK_UART3 84 macro
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| H A D | rk3288_cru.c | 692 MUX(SCLK_UART3, "sclk_uart3", uart3_p, 0,
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| H A D | rk3399_cru.c | 1015 MUX(SCLK_UART3, "clk_uart3", uart3_p, 0,
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| H A D | rk3568_cru.c | 1259 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_sel", 28, 7),
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| /src/sys/contrib/device-tree/src/arm/rockchip/ |
| H A D | rk3xxx.dtsi | 436 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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| H A D | rv1126.dtsi | 484 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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| /src/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | s5pv210.dtsi | 358 <&clocks SCLK_UART3>;
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| /src/sys/contrib/device-tree/src/arm64/exynos/ |
| H A D | exynos7.dtsi | 317 <&clock_peric1 SCLK_UART3>;
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| /src/sys/contrib/device-tree/src/arm64/rockchip/ |
| H A D | rk3528.dtsi | 631 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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| H A D | rk3368.dtsi | 355 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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| H A D | rk3562.dtsi | 804 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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