| /src/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.cpp | 51 MVT RegisterVT = TLI.getRegisterType(Ctx, VT); in computeLegalValueVTs() local
53 ValueVTs.push_back(RegisterVT); in computeLegalValueVTs()
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| /src/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVISelLowering.h | 63 std::optional<MVT> RegisterVT = std::nullopt) const override {
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| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1065 MVT &RegisterVT, in getVectorTypeBreakdownMVT() argument
1109 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1451 MVT RegisterVT; in computeRegisterProperties() local
1454 NumIntermediates, RegisterVT, this); in computeRegisterProperties()
1458 RegisterTypeForVT[i] = RegisterVT; in computeRegisterProperties()
1520 MVT &RegisterVT) const { in getVectorTypeBreakdown()
1534 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
1565 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdown()
1592 RegisterVT = DestVT; in getVectorTypeBreakdown()
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| /src/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 443 std::optional<MVT> RegisterVT) const override { in getNumRegisters() argument
445 if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped) in getNumRegisters()
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 110 MVT RegisterVT; in getRegisterTypeForCallingConv() local
112 std::tie(RegisterVT, NumRegisters) = in getRegisterTypeForCallingConv()
114 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getRegisterTypeForCallingConv()
115 return RegisterVT; in getRegisterTypeForCallingConv()
144 MVT RegisterVT; in getNumRegistersForCallingConv() local
146 std::tie(RegisterVT, NumRegisters) = in getNumRegistersForCallingConv()
148 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getNumRegistersForCallingConv()
174 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
181 RegisterVT = MVT::i8; in getVectorTypeBreakdownForCallingConv()
190 RegisterVT = MVT::v32i8; in getVectorTypeBreakdownForCallingConv()
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| H A D | X86ISelLowering.h | 1538 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| /src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 388 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs() local
392 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
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| H A D | SelectionDAGBuilder.cpp | 356 MVT RegisterVT; in getCopyFromPartsVector() local
363 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
367 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
372 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyFromPartsVector()
373 assert(RegisterVT.getSizeInBits() == in getCopyFromPartsVector()
761 MVT RegisterVT; in getCopyToPartsVector() local
767 RegisterVT); in getCopyToPartsVector()
771 NumIntermediates, RegisterVT); in getCopyToPartsVector()
776 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyToPartsVector()
865 MVT RegisterVT = in RegsForValue() local
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| H A D | FastISel.cpp | 1015 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo() local
1019 MyFlags.VT = RegisterVT; in lowerCallTo()
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| H A D | SelectionDAG.cpp | 2477 MVT RegisterVT; in getReducedAlign() local
2480 NumIntermediates, RegisterVT); in getReducedAlign()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1174 MVT &RegisterVT) const;
1181 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
1183 RegisterVT); in getVectorTypeBreakdownForCallingConv()
1722 MVT RegisterVT; in getRegisterType() local
1725 NumIntermediates, RegisterVT); in getRegisterType()
1726 return RegisterVT; in getRegisterType()
1747 std::optional<MVT> RegisterVT = std::nullopt) const {
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| /src/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.h | 645 std::optional<MVT> RegisterVT) const override;
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| H A D | NVPTXISelLowering.cpp | 3141 std::optional<MVT> RegisterVT = std::nullopt) const { in getNumRegisters() argument
3142 if (VT == MVT::i128 && RegisterVT == MVT::i128) in getNumRegisters()
3144 return TargetLoweringBase::getNumRegisters(Context, VT, RegisterVT); in getNumRegisters()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1191 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT); in analyzeFormalArgumentsCompute() local
1199 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1203 } else if (ArgVT.isVector() && RegisterVT.isVector() && in analyzeFormalArgumentsCompute()
1204 ArgVT.getScalarType() == RegisterVT.getScalarType()) { in analyzeFormalArgumentsCompute()
1205 assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements()); in analyzeFormalArgumentsCompute()
1209 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1217 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1221 if (RegisterVT.isInteger()) { in analyzeFormalArgumentsCompute()
1223 } else if (RegisterVT.isVector()) { in analyzeFormalArgumentsCompute()
1224 assert(!RegisterVT.getScalarType().isFloatingPoint()); in analyzeFormalArgumentsCompute()
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| H A D | SIISelLowering.h | 45 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | SIISelLowering.cpp | 1062 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
1072 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
1075 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16; in getVectorTypeBreakdownForCallingConv()
1076 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1083 RegisterVT = ScalarVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
1084 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1091 RegisterVT = MVT::i16; in getVectorTypeBreakdownForCallingConv()
1099 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
1106 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
1107 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
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| /src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 308 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | MipsISelLowering.cpp | 126 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
129 RegisterVT = IntermediateVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
135 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdownForCallingConv()
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| /src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 550 MVT &RegisterVT) const override;
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| H A D | RISCVISelLowering.cpp | 2370 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
2372 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
2377 if (RV64LegalI32 && Subtarget.is64Bit() && RegisterVT == MVT::i32) in getVectorTypeBreakdownForCallingConv()
2378 RegisterVT = MVT::i64; in getVectorTypeBreakdownForCallingConv()
22079 MVT RegisterVT = OutArg.VT; in constructArgInfos() local
22082 if (!RegisterVT.isVector()) in constructArgInfos()
22085 if (RegisterVT.isFixedLengthVector()) in constructArgInfos()
22086 RegisterVT = TLI->getContainerForFixedLengthVector(RegisterVT); in constructArgInfos()
22088 if (!FirstVMaskAssigned && RegisterVT.getVectorElementType() == MVT::i1) { in constructArgInfos()
22089 RVVArgInfos.push_back({1, RegisterVT, true}); in constructArgInfos()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 1021 MVT &RegisterVT) const override;
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| H A D | AArch64ISelLowering.cpp | 28632 MVT RegisterVT; in getRegisterTypeForCallingConv() local
28635 RegisterVT); in getRegisterTypeForCallingConv()
28636 return RegisterVT; in getRegisterTypeForCallingConv()
28655 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
28657 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
28658 if (!RegisterVT.isFixedLengthVector() || in getVectorTypeBreakdownForCallingConv()
28659 RegisterVT.getFixedSizeInBits() <= 128) in getVectorTypeBreakdownForCallingConv()
28663 assert(IntermediateVT == RegisterVT && "Unexpected VT mismatch!"); in getVectorTypeBreakdownForCallingConv()
28664 assert(RegisterVT.getFixedSizeInBits() % 128 == 0 && "Unexpected size!"); in getVectorTypeBreakdownForCallingConv()
28668 if (RegisterVT.getSizeInBits() * NumRegs != VT.getSizeInBits()) { in getVectorTypeBreakdownForCallingConv()
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