| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ ! |
| H A D | RegisterBankInfo.h | 61 const RegisterBank *RegBank;
67 const RegisterBank &RegBank) in PartialMapping()
389 const RegisterBank **RegBanks;
426 RegisterBankInfo(const RegisterBank **RegBanks, unsigned NumRegBanks,
440 const RegisterBank &getRegBank(unsigned ID) { in getRegBank()
472 const RegisterBank &RegBank) const;
480 const RegisterBank &RegBank) const;
553 const RegisterBank *
585 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank()
599 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
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| H A D | RegisterBank.h | 28 class RegisterBank {
39 constexpr RegisterBank(unsigned ID, const char *Name, in RegisterBank() function
65 bool operator==(const RegisterBank &OtherRB) const;
66 bool operator!=(const RegisterBank &OtherRB) const {
83 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
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| /src/contrib/llvm-project/llvm/lib/CodeGen/ ! |
| H A D | RegisterBank.cpp | 23 bool RegisterBank::verify(const RegisterBankInfo &RBI, in verify()
52 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
56 bool RegisterBank::operator==(const RegisterBank &OtherRB) const { in operator ==()
66 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump()
71 void RegisterBank::print(raw_ostream &OS, bool IsForDebug, in print()
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| H A D | RegisterBankInfo.cpp | 56 RegisterBankInfo::RegisterBankInfo(const RegisterBank **RegBanks, in RegisterBankInfo()
73 const RegisterBank &RegBank = getRegBank(Idx); in verify()
83 const RegisterBank *
94 if (auto *RB = dyn_cast_if_present<const RegisterBank *>(RegClassOrBank)) in getRegBank()
114 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints( in getRegBankFromConstraints()
127 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); in getRegBankFromConstraints()
142 const RegisterBank *RB = cast<const RegisterBank *>(RegClassOrBank); in constrainGenericRegister()
198 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
202 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr; in getInstrMappingImpl()
243 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
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| /src/contrib/llvm-project/llvm/utils/TableGen/ ! |
| H A D | RegisterBankEmitter.cpp | 28 class RegisterBank { class
43 RegisterBank(const Record &TheDef, unsigned NumModeIds) in RegisterBank() function in __anon854007cb0111::RegisterBank
113 const std::vector<RegisterBank> &Banks);
115 const std::vector<RegisterBank> &Banks);
117 std::vector<RegisterBank> &Banks);
131 const std::vector<RegisterBank> &Banks) { in emitHeader()
150 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
217 raw_ostream &OS, StringRef TargetName, std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
300 std::vector<RegisterBank> Banks; in run()
303 RegisterBank Bank(*V, CGH.getNumModeIds()); in run()
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| /src/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ ! |
| H A D | PPCRegisterBanks.td | 15 def GPRRegBank : RegisterBank<"GPR", [G8RC, G8RC_NOX0]>;
17 def FPRRegBank : RegisterBank<"FPR", [VSSRC]>;
19 def VECRegBank : RegisterBank<"VEC", [VSRC]>;
21 def CRRegBank : RegisterBank<"CR", [CRRC]>;
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| H A D | PPCRegisterBankInfo.cpp | 33 const RegisterBank &
229 const RegisterBank &DstRB = DstIsGPR ? PPC::GPRRegBank : PPC::VECRegBank; in getInstrMapping()
230 const RegisterBank &SrcRB = SrcIsGPR ? PPC::GPRRegBank : PPC::VECRegBank; in getInstrMapping()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ ! |
| H A D | AMDGPURegisterBanks.td | 9 def SGPRRegBank : RegisterBank<"SGPR",
13 def VGPRRegBank : RegisterBank<"VGPR",
18 def VCCRegBank : RegisterBank <"VCC", [SReg_1]>;
20 def AGPRRegBank : RegisterBank <"AGPR",
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| H A D | AMDGPURegisterBankInfo.h | 168 bool isDivergentRegBank(const RegisterBank *RB) const override;
170 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
174 const RegisterBank *CurBank = nullptr) const override;
176 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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| H A D | AMDGPURegisterBankInfo.cpp | 103 const RegisterBank *NewBank;
108 MachineRegisterInfo &MRI_, const RegisterBank *RB) in ApplyRegBankMapping()
131 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI); in applyBank()
158 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI); in applyBank()
172 const RegisterBank *RB = NewBank; in applyBank()
221 static bool isVectorRegisterBank(const RegisterBank &Bank) { in isVectorRegisterBank()
226 bool AMDGPURegisterBankInfo::isDivergentRegBank(const RegisterBank *RB) const { in isDivergentRegBank()
230 unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst, in copyCost()
231 const RegisterBank &Src, in copyCost()
263 const RegisterBank *CurBank) const { in getBreakDownCost()
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| /src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ ! |
| H A D | RISCVRegisterBanks.td | 13 def GPRBRegBank : RegisterBank<"GPRB", [GPR]>;
16 def FPRBRegBank : RegisterBank<"FPRB", [FPR64]>;
19 def VRBRegBank : RegisterBank<"VRB", [VRM8]>;
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ ! |
| H A D | AArch64RegisterBankInfo.h | 66 unsigned ValLength, const RegisterBank &RB);
149 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
152 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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| H A D | AArch64RegisterBankInfo.cpp | 57 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
62 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
67 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
220 unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A, in copyCost()
221 const RegisterBank &B, in copyCost()
241 const RegisterBank &
712 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
713 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
737 const RegisterBank &DstRB = in getInstrMapping()
739 const RegisterBank &SrcRB = in getInstrMapping()
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ ! |
| H A D | X86RegisterBanks.td | 13 def GPRRegBank : RegisterBank<"GPR", [GR64]>;
16 def VECRRegBank : RegisterBank<"VECR", [VR512]>;
19 def PSRRegBank : RegisterBank<"PSR", [RFP32, RFP64, RFP80]>;
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ ! |
| H A D | AArch64RegisterBanks.td | 13 def GPRRegBank : RegisterBank<"GPR", [XSeqPairsClass]>;
16 def FPRRegBank : RegisterBank<"FPR", [QQQQ, ZPR]>;
19 def CCRegBank : RegisterBank<"CC", [CCR]>;
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/ ! |
| H A D | MIParser.h | 31 class RegisterBank; variable
46 const RegisterBank *RegBank;
53 using Name2RegBankMap = StringMap<const RegisterBank *>;
151 const RegisterBank *getRegBank(StringRef Name);
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| /src/contrib/llvm-project/llvm/lib/Target/Mips/ ! |
| H A D | MipsRegisterBanks.td | 12 def GPRBRegBank : RegisterBank<"GPRB", [GPR32]>;
14 def FPRBRegBank : RegisterBank<"FPRB", [FGR64, AFGR64, MSA128D]>;
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| /src/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/ ! |
| H A D | RegisterBank.td | 1 //===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===//
12 class RegisterBank<string name, list<RegisterClass> classes> {
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ ! |
| H A D | ARMRegisterBanks.td | 12 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;
13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
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| H A D | ARMRegisterBankInfo.h | 35 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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| /src/contrib/llvm-project/llvm/lib/Target/SPIRV/ ! |
| H A D | SPIRVRegisterBanks.td | 12 def TYPERegBank : RegisterBank<"TYPEBank", [TYPE]>;
13 def IDRegBank : RegisterBank<"IDBank", [ID, ID64, fID, fID64, pID32, pID64, vID, vfID, vpID32, vpID…
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| H A D | SPIRVRegisterBankInfo.cpp | 27 const RegisterBank &
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| H A D | SPIRVRegisterBankInfo.h | 34 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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| /src/contrib/llvm-project/llvm/lib/Target/X86/GISel/ ! |
| H A D | X86InstructionSelector.cpp | 75 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
130 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
172 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass()
213 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
262 const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank); in selectDebugInstr()
281 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
285 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
450 const RegisterBank &RB, in getLoadStoreOp()
570 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
802 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ ! |
| H A D | CSEInfo.h | 166 class RegisterBank; variable
183 const GISelInstProfileBuilder &addNodeIDRegType(const RegisterBank *RB) const;
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