| /src/contrib/arm-optimized-routines/math/aarch64/experimental/ |
| H A D | erfc_1u8.c | 28 #define Q8 0x1.2p0 macro
110 double p9 = fma (Q8 * r, p8, p7) * R8; in erfc()
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| /src/lib/msun/bsdsrc/ |
| H A D | b_tgamma.c | 177 Q8 = 6.1327550747244396e-6; variable
186 z * (Q6 + z * (Q7 + z * Q8))))))); in ratfun_gam()
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| /src/lib/msun/ld80/ |
| H A D | b_tgammal.c | 200 #define Q8 (Q8u.e) macro
209 z * (Q6 + z * (Q7 + z * Q8))))))); in ratfun_gam()
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| /src/sys/contrib/device-tree/src/arm/allwinner/ |
| H A D | sun8i-a33-q8-tablet.dts | 48 model = "Q8 A33 Tablet";
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| H A D | sun8i-a33-et-q8-v1.6.dts | 48 model = "Q8 A33 Tablet";
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| H A D | sun8i-a33-ippo-q8h-v1.2.dts | 48 model = "Q8 A33 Tablet";
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| H A D | sun8i-a23-q8-tablet.dts | 48 model = "Q8 A23 Tablet";
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| H A D | sun8i-a23-ippo-q8h-v5.dts | 48 model = "Q8 A23 Tablet";
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| H A D | sun5i-a13-q8-tablet.dts | 48 model = "Q8 A13 Tablet";
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| H A D | sun8i-a23-ippo-q8h-v1.2.dts | 48 model = "Q8 A23 Tablet";
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| H A D | sun8i-q8-common.dtsi | 68 * Q8 boards use various PL# pins as wifi-en. On other boards
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| H A D | sun8i-v3s-netcube-kumquat.dts | 200 "I6", "I7", "Q7", "Q8",
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 125 case AArch64::Q8: in isOdd()
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| H A D | AArch64RegisterInfo.td | 426 def Q8 : AArch64Reg<8, "q8", [D8], ["v8", ""]>, DwarfRegAlias<B8>;
866 def Z8 : AArch64Reg<8, "z8", [Q8]>, DwarfRegNum<[104]>;
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| H A D | AArch64CallingConvention.td | 593 // must (additionally) preserve full Q8-Q23 registers
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| /src/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 91 SP::Q0, SP::Q8, ~0U, ~0U,
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.td | 169 def Q8 : ARMReg< 8, "q8", [D16, D17]>;
492 // Allocate non-VFP2 aliases Q8-Q15 first.
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 320 {codeview::RegisterId::ARM_NQ8, ARM::Q8}, in initLLVMToCVRegMapping()
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| H A D | ARMMCCodeEmitter.cpp | 563 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: in getMachineOpValue()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 213 {codeview::RegisterId::ARM64_Q8, AArch64::Q8}, in initLLVMToCVRegMapping()
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| H A D | AArch64InstPrinter.cpp | 1519 case AArch64::Q7: Reg = AArch64::Q8; break; in getNextVectorRegister()
1520 case AArch64::Q8: Reg = AArch64::Q9; break; in getNextVectorRegister()
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| /src/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.td | 289 def Q8 : Rq< 1, "f32", [D16, D17]>;
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| /src/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/ |
| H A D | VEDisassembler.cpp | 94 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
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| /src/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 182 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
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| /src/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 127 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
|