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Searched refs:Pin (Results 1 – 25 of 94) sorted by relevance

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/src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mq-nitrogen.dts369 MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
370 MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
371 MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
372 MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
373 MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
374 MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
375 MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
376 MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
377 MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
378 MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
[all …]
/src/sys/contrib/device-tree/src/arm/amlogic/
H A Dmeson8b-odroidc1.dts234 "J2 Header Pin 35", "J2 Header Pin 36",
235 "J2 Header Pin 32", "J2 Header Pin 31",
236 "J2 Header Pin 29", "J2 Header Pin 18",
237 "J2 Header Pin 22", "J2 Header Pin 16",
238 "J2 Header Pin 23", "J2 Header Pin 21",
239 "J2 Header Pin 19", "J2 Header Pin 33",
240 "J2 Header Pin 8", "J2 Header Pin 10",
241 "J2 Header Pin 15", "J2 Header Pin 13",
242 "J2 Header Pin 24", "J2 Header Pin 26",
245 "J2 Header Pin 7", "", "J2 Header Pin 12",
[all …]
/src/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi6220-hikey.dts356 * Pin assignments taken from LeMaker and CircuitCo Schematics
384 "GPIO-A", /* LSEC Pin 23: GPIO2_0 */
385 "GPIO-B", /* LSEC Pin 24: GPIO2_1 */
386 "GPIO-C", /* LSEC Pin 25: GPIO2_2 */
387 "GPIO-D", /* LSEC Pin 26: GPIO2_3 */
388 "GPIO-E", /* LSEC Pin 27: GPIO2_4 */
390 "GPIO-H"; /* LSEC Pin 30: GPIO2_7 */
405 "[UART1_RxD]", /* LSEC Pin 11: UART3_RX */
406 "[UART1_TxD]", /* LSEC Pin 13: UART3_TX */
408 "[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */
[all …]
/src/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588-friendlyelec-cm3588-nas.dts252 "Pin 10 [UART0_RX_M0]", "Pin 08 [UART0_TX_M0/PWM4_M0]", "Pin 32 [PWM5_M1]", "",
261 "Pin 27 [UART6_RX_M1]", "Pin 28 [UART6_TX_M1]", "", "",
262 "USB2 Type-A [USB2_PWREN]", "", "", "Pin 15",
264 …"Pin 26", "Pin 21 [SPI0_MISO_M2]", "Pin 19 [SPI0_MOSI_M2/UART4_RX_M2]", "Pin 23 [SPI0_CLK_M2/UART4…
265 …"Pin 24 [SPI0_CS0_M2/UART7_RX_M2]", "Pin 22 [SPI0_CS1_M0/UART7_TX_M2]", "", "CSI-Pin 14 [MIPI_CAM2…
271 "", "HDMI-in detect [HDMIIRX_DET_L]", "Pin 05 [I2C8_SCL_M2]", "Pin 03 [I2C8_SDA_M2]";
283 "", "CSI-Pin 11 [MIPI_CAM2_RESET_L]", "CSI-Pin 12 [MIPI_CAM2_PDN_L]", "",
293 …"Pin 35 [SPI4_MISO_M1/PWM10_M0]", "Pin 38 [SPI4_MOSI_M1]", "Pin 40 [SPI4_CLK_M1/UART8_TX_M1]", "Pi…
294 "Pin 37 [SPI4_CS1_M1]", "USB3-A #2 [USB3_2_PWREN]", "DSI-Pin 12 [LCD_RST]", "Buzzer [PWM8_M0]",
296 "Pin 33 [PWM9_M0]", "DSI-Pin 10 [PWM2_M1/LCD_BL]", "Pin 07", "Pin 16",
[all …]
/src/sys/contrib/device-tree/Bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt64 pmu-nc Pin not driven by any PM function
65 pmu-low Pin driven low (0)
66 pmu-high Pin driven high (1)
67 pmic(sdi) Pin is used for PMIC SDI
68 cpu-pwr-down Pin is used for CPU_PWRDWN
69 standby-pwr-down Pin is used for STBY_PWRDWN
70 core-pwr-good Pin is used for CORE_PWR_GOOD (Pins 0-7 only)
71 cpu-pwr-good Pin is used for CPU_PWR_GOOD (Pins 8-15 only)
72 bat-fault Pin is used for BATTERY_FAULT
73 ext0-wakeup Pin is used for EXT0_WU
[all …]
H A Drenesas,rza1-pinctrl.txt1 Renesas RZ/A1 combined Pin and GPIO controller
3 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,
5 Pin multiplexing and GPIO configuration is performed on a per-pin basis
11 Pin controller node
25 Pin controller node for RZ/A1H SoC (r7s72100)
39 - Pin multiplexing sub-nodes:
140 Pin #0 on port #3 is configured as alternate function #6.
141 Pin #2 on port #3 is configured as alternate function #4.
152 Pin #4 on port #1 is configured as alternate function #1.
153 Pin #5 on port #1 is configured as alternate function #1.
[all …]
H A Drenesas,rza2-pinctrl.txt1 Renesas RZ/A2 combined Pin and GPIO controller
3 The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller.
4 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
9 Pin controller node
25 Example: Pin controller node for RZ/A2M SoC (r7s9210)
42 - Pin multiplexing sub-nodes:
H A Dcnxt,cx92755-pinctrl.txt1 Conexant Digicolor CX92755 General Purpose Pin Mapping
7 === Pin Controller Node ===
12 - reg: Base address of the General Purpose Pin Mapping register block and the
34 === Pin Configuration Node ===
44 === Pin Group Node ===
56 Required Pin Group Node Properties:
H A Dberlin,pinctrl.txt1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
H A Drenesas,pfc-pinctrl.txt1 * Renesas Pin Function Controller (GPIO and Pin Mux/Config)
3 The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0,
7 Pin Control
64 Pin configuration nodes contain pin configuration properties, either directly
77 Pin Configuration Node Properties:
H A Dti,da850-pupd.txt1 * Pin configuration for TI DA850/OMAP-L138/AM18x
15 Pin Group Node Properties:
H A Dfsl,imx7ulp-pinctrl.txt41 /* Pin Controller Node */
46 /* Pin Configuration Node */
H A Dsamsung-pinctrl.txt1 Samsung GPIO and Pin Mux/Config controller
3 Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
50 - Pin banks as child nodes: Pin banks of the controller are represented by child
65 - Pin number: is a value between 0 to 7.
69 - Pin mux/config groups as child nodes: The pin mux (selecting pin function
220 /* Pin bank without external interrupts */
228 /* Pin bank with external GPIO or muxed wake-up interrupts */
239 /* Pin bank with external direct wake-up interrupts */
H A Dbrcm,nsp-gpio.txt34 3 Pin-control base pin offset.
40 in the node apply to. Pin names are "gpio-<pin>"
/src/sys/contrib/device-tree/Bindings/net/
H A Dmdio-mux-gpio.txt46 interrupts = <10 8>; /* Pin 10, active low */
55 interrupts = <10 8>; /* Pin 10, active low */
64 interrupts = <10 8>; /* Pin 10, active low */
73 interrupts = <10 8>; /* Pin 10, active low */
89 interrupts = <12 8>; /* Pin 12, active low */
98 interrupts = <12 8>; /* Pin 12, active low */
107 interrupts = <12 8>; /* Pin 12, active low */
116 interrupts = <12 8>; /* Pin 12, active low */
H A Dmdio-mux.txt56 interrupts = <10 8>; /* Pin 10, active low */
65 interrupts = <10 8>; /* Pin 10, active low */
74 interrupts = <10 8>; /* Pin 10, active low */
83 interrupts = <10 8>; /* Pin 10, active low */
99 interrupts = <12 8>; /* Pin 12, active low */
108 interrupts = <12 8>; /* Pin 12, active low */
117 interrupts = <12 8>; /* Pin 12, active low */
126 interrupts = <12 8>; /* Pin 12, active low */
/src/sys/contrib/device-tree/Bindings/sound/
H A Drt274.txt18 * DMIC1 Pin
19 * DMIC2 Pin
23 * HPO Pin
H A Dcs4265.txt20 codec_ad0_high: cs4265@4f { /* AD0 Pin is high */
26 codec_ad0_low: cs4265@4e { /* AD0 Pin is low */
/src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ull-colibri-aster.dts52 /* Pin already used by atmel_mxt_ts touchscreen */
58 /* Pin already used by atmel_mxt_ts touchscreen */
H A Dimx6ull-colibri-wifi-aster.dts52 /* Pin already used by atmel_mxt_ts touchscreen */
58 /* Pin already used by atmel_mxt_ts touchscreen */
H A Dimx6ull-colibri-iris-v2.dts97 /* Pin already used by atmel_mxt_ts touchscreen */
103 /* Pin already used by atmel_mxt_ts touchscreen */
/src/sys/contrib/device-tree/Bindings/arm/hisilicon/
H A Dhisilicon-low-pin-count.txt1 Hisilicon Hip06 Low Pin Count device
2 Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
/src/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/qe/
H A Dpincfg.txt1 * Pin configuration nodes
22 - assignment : function number of the pin according to the Pin Assignment
/src/sys/contrib/device-tree/src/arm/marvell/
H A Dorion5x-netgear-wnr854t.dts250 /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
/src/sys/contrib/device-tree/Bindings/display/tilcdc/
H A Dpanel.txt6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt

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