| /src/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCSchedule.cpp | 23 static_assert(std::is_trivial_v<MCSchedModel>,
25 const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
42 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI, in computeInstrLatency()
58 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI, in computeInstrLatency()
64 return MCSchedModel::computeInstrLatency(STI, SCDesc); in computeInstrLatency()
69 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI, in computeInstrLatency()
84 return MCSchedModel::computeInstrLatency(STI, *SCDesc); in computeInstrLatency()
90 MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI, in getReciprocalThroughput()
93 const MCSchedModel &SM = STI.getSchedModel(); in getReciprocalThroughput()
112 MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI, in getReciprocalThroughput()
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| H A D | MCSubtargetInfo.cpp | 217 CPUSchedModel = &MCSchedModel::Default; in InitMCProcessorInfo()
310 const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const { in getSchedModelForCPU()
322 return MCSchedModel::Default; in getSchedModelForCPU()
330 const MCSchedModel &SchedModel = getSchedModelForCPU(CPU); in getInstrItineraryForCPU()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetSchedule.h | 33 MCSchedModel SchedModel;
49 TargetSchedModel() : SchedModel(MCSchedModel::Default) {} in TargetSchedModel()
74 const MCSchedModel *getMCSchedModel() const { return &SchedModel; } in getMCSchedModel()
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| /src/contrib/llvm-project/llvm/tools/llvm-mca/Views/ |
| H A D | InstructionInfoView.cpp | 114 const MCSchedModel &SM = STI.getSchedModel(); in collectData()
136 IIVDEntry.Latency = MCSchedModel::computeInstrLatency(STI, SCDesc); in collectData()
138 IIVDEntry.Latency += MCSchedModel::getForwardingDelayCycles( in collectData()
140 IIVDEntry.RThroughput = MCSchedModel::getReciprocalThroughput(STI, SCDesc); in collectData()
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| H A D | SummaryView.h | 40 const llvm::MCSchedModel &SM;
77 SummaryView(const llvm::MCSchedModel &Model, llvm::ArrayRef<llvm::MCInst> S,
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| H A D | ResourcePressureView.cpp | 27 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in ResourcePressureView()
69 const MCSchedModel &SM) { in printColumnNames()
109 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in printResourcePressurePerIter()
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| H A D | RetireControlUnitStatistics.h | 50 RetireControlUnitStatistics(const MCSchedModel &SM);
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| H A D | BottleneckAnalysis.h | 97 const MCSchedModel &SM;
139 PressureTracker(const MCSchedModel &Model);
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| H A D | SchedulerStatistics.h | 48 const llvm::MCSchedModel &SM;
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| H A D | RetireControlUnitStatistics.cpp | 20 RetireControlUnitStatistics::RetireControlUnitStatistics(const MCSchedModel &SM) in RetireControlUnitStatistics()
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| /src/contrib/llvm-project/llvm/include/llvm/MCA/Stages/ |
| H A D | InstructionTables.h | 29 const MCSchedModel &SM;
34 InstructionTables(const MCSchedModel &Model) in InstructionTables()
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| /src/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 59 const MCSchedModel *SchedModel;
87 const MCSchedModel *CPUSchedModel;
160 const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
163 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; } in getSchedModel()
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| H A D | MCInstrItineraries.h | 112 MCSchedModel SchedModel =
113 MCSchedModel::Default; ///< Basic machine properties.
121 InstrItineraryData(const MCSchedModel &SM, const InstrStage *S, in InstrItineraryData()
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| H A D | MCSchedule.h | 253 struct MCSchedModel { struct
393 static const MCSchedModel Default; argument
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| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 241 return capLatency(MCSchedModel::computeInstrLatency(*STI, SCDesc)); in computeInstrLatency()
312 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
317 return MCSchedModel::getReciprocalThroughput(*STI, *resolveSchedClass(MI)); in computeReciprocalThroughput()
326 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
331 return MCSchedModel::getReciprocalThroughput(*STI, SCDesc); in computeReciprocalThroughput()
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| /src/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/ |
| H A D | LSUnit.h | 222 LSUnitBase(const MCSchedModel &SM, unsigned LoadQueueSize,
443 LSUnit(const MCSchedModel &SM) in LSUnit()
445 LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ) in LSUnit()
447 LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ, bool AssumeNoAlias) in LSUnit()
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| H A D | RegisterFile.h | 229 void initialize(const MCSchedModel &SM, unsigned NumRegs);
232 RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
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| H A D | Scheduler.h | 157 Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu) in Scheduler()
160 Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu, in Scheduler()
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| H A D | RetireControlUnit.h | 80 RetireControlUnit(const MCSchedModel &SM);
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| /src/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Support.h | 95 void computeProcResourceMasks(const MCSchedModel &SM,
109 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
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| /src/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | Support.cpp | 40 void computeProcResourceMasks(const MCSchedModel &SM, in computeProcResourceMasks()
83 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth, in computeBlockRThroughput()
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| H A D | Context.cpp | 34 const MCSchedModel &SM = STI.getSchedModel(); in createDefaultPipeline()
75 const MCSchedModel &SM = STI.getSchedModel(); in createInOrderPipeline()
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| H A D | InstrBuilder.cpp | 38 const MCSchedModel &SM = STI.getSchedModel(); in InstrBuilder()
47 const MCSchedModel &SM = STI.getSchedModel(); in initializeUsedResources()
233 int Latency = MCSchedModel::computeInstrLatency(STI, SCDesc); in computeMaxLatency()
271 const MCSchedModel &SM = STI.getSchedModel(); in populateWrites()
545 const MCSchedModel &SM = STI.getSchedModel(); in getVariantSchedClassID()
568 const MCSchedModel &SM = STI.getSchedModel(); in createInstrDescImpl()
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| /src/contrib/llvm-project/llvm/tools/llvm-mca/ |
| H A D | PipelinePrinter.cpp | 52 const MCSchedModel &SM = STI.getSchedModel(); in getJSONSimulationParameters()
82 const MCSchedModel &SM = STI.getSchedModel(); in getJSONTargetInfo()
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| /src/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 64 RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri, in RegisterFile()
72 void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) { in initialize()
507 const MCSchedModel &SM = STI.getSchedModel(); in collectWrites()
574 const MCSchedModel &SM = STI.getSchedModel(); in checkRAWHazards()
638 const MCSchedModel &SM = STI.getSchedModel(); in addRegisterRead()
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