Searched refs:CSR_BASE (Results 1 – 1 of 1) sorted by relevance
27 #define CSR_BASE (0x000) macro29 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */30 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */31 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */32 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */33 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/34 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */35 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/36 #define CSR_GP_CNTRL (CSR_BASE+0x024)37 #define CSR_FUNC_SCRATCH (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */[all …]