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Searched refs:m2 (Results 1 – 21 of 21) sorted by relevance

/qemu/tests/tcg/xtensa/
H A Dtest_mac16.S51 test_mulxx mul.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f
97 test_mulxxx mula.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, +
114 test_mulxxx muls.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, -
147 lddec m2, a2
150 rsr a3, m2
203 test_mulxxx_ld mula.dd, ldinc, 3, m2, a2, m1, m2, \
207 rsr a2, m2
232 test_mulxxx_ld mula.dd, lddec, 3, m2, a2, m1, m2, \
236 rsr a2, m2
/qemu/util/
H A Diova-tree.c60 const DMAMap *m1 = a, *m2 = b; in iova_tree_compare() local
62 if (m1->iova > m2->iova + m2->size) { in iova_tree_compare()
66 if (m1->iova + m1->size < m2->iova) { in iova_tree_compare()
263 const DMAMap *m1 = a, *m2 = b; in gpa_tree_compare() local
265 if (m1->translated_addr > m2->translated_addr + m2->size) { in gpa_tree_compare()
269 if (m1->translated_addr + m1->size < m2->translated_addr) { in gpa_tree_compare()
/qemu/include/fpu/
H A Dsoftfloat-macros.h541 uint64_t m0, m1, m2, n1, n2; in mul128To256() local
543 mul64To128(a1, b0, &m1, &m2); in mul128To256()
548 add192( 0, m1, m2, 0, n1, n2, &m0, &m1, &m2); in mul128To256()
549 add192(m0, m1, m2, z0, z1, z2, z0Ptr, z1Ptr, z2Ptr); in mul128To256()
/qemu/docs/system/arm/
H A Dbananapi_m2u.rst69 -dtb /path/to/linux/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dtb
92 openwrt-22.03.3-sunxi-cortexa7-sinovoip_bananapi-m2-ultra-ext4-sdcard.img \
103 -sd openwrt-22.03.3-sunxi-cortexa7-sinovoip_bananapi-m2-ultra-ext4-sdcard.img
/qemu/target/s390x/tcg/
H A Dfpu_helper.c847 uint32_t HELPER(tceb)(CPUS390XState *env, uint64_t f1, uint64_t m2) in DEF_FLOAT_DCMASK()
849 return (m2 & float32_dcmask(env, f1)) != 0; in DEF_FLOAT_DCMASK()
853 uint32_t HELPER(tcdb)(CPUS390XState *env, uint64_t v1, uint64_t m2) in HELPER()
855 return (m2 & float64_dcmask(env, v1)) != 0; in HELPER()
859 uint32_t HELPER(tcxb)(CPUS390XState *env, Int128 a, uint64_t m2) in HELPER()
861 return (m2 & float128_dcmask(env, ARG128(a))) != 0; in HELPER()
/qemu/hw/display/
H A Dvhost-user-gpu.c283 VhostUserGpuDMABUFScanout2 *m2 = &msg->payload.dmabuf_scanout2; in vhost_user_gpu_handle_display() local
284 modifier = m2->modifier; in vhost_user_gpu_handle_display()
/qemu/tcg/tci/
H A Dtcg-target.c.inc195 TCGReg r0, TCGReg r1, TCGArg m2)
199 tcg_debug_assert(m2 == extract32(m2, 0, 16));
203 insn = deposit32(insn, 16, 16, m2);
/qemu/target/xtensa/core-dc232b/
H A Dgdb-config.c.inc120 XTREG(49, 196, 32, 4, 4, 0x0222, 0x0006, -1, 2, 0x1100, m2,
H A Dxtensa-modules.c.inc11648 { "rsr.m2", 196 /* xt_iclass_rsr.m2 */,
11651 { "wsr.m2", 197 /* xt_iclass_wsr.m2 */,
11654 { "xsr.m2", 198 /* xt_iclass_xsr.m2 */,
12348 return 300; /* xsr.m2 */
12540 return 298; /* rsr.m2 */
12677 return 299; /* wsr.m2 */
/qemu/target/xtensa/core-dc233c/
H A Dgdb-config.c.inc74 XTREG(49, 196, 32, 4, 4, 0x0222, 0x0006, -1, 2, 0x1100, m2, 0, 0, 0, 0, 0, 0)
H A Dxtensa-modules.c.inc12296 { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
12299 { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
12302 { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
/qemu/tcg/
H A Dtci.c113 TCGReg *r1, MemOpIdx *m2) in tci_args_rrm() argument
117 *m2 = extract32(insn, 16, 16); in tci_args_rrm()
/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc71 XTREG( 47,188,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc11665 { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
11668 { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
11671 { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
/qemu/target/xtensa/core-test_kc705_be/
H A Dgdb-config.c.inc73 XTREG( 50,200,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc33815 { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
33818 { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
33821 { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
/qemu/target/arm/tcg/
H A Dmve_helper.c1327 int64_t m2 = (int64_t)c * d; in do_vqdmladh_w() local
1341 if (sadd64_overflow(m1, m2, &r) || in do_vqdmladh_w()
1368 int64_t m2 = (int64_t)c * d; in do_vqdmlsdh_w() local
1371 if (ssub64_overflow(m1, m2, &r) || in do_vqdmlsdh_w()
1555 int64_t m2 = (int64_t)c << 31; in do_vqdmlah_w() local
1557 if (sadd64_overflow(m1, m2, &r) || in do_vqdmlah_w()
H A Dvec_helper.c854 TYPED m2 = m_indexed[i * 4 + 2]; \ in DO_DOT()
860 n[i * 4 + 2] * m2 + \ in DO_DOT()
/qemu/target/xtensa/core-de233_fpu/
H A Dgdb-config.c.inc72 XTREG( 49,196,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc16924 { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
16927 { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
16930 { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
/qemu/target/xtensa/
H A Dtranslate.c1761 TCGv_i32 m2 = gen_mac16_m(arg[off + 1].in, in translate_mac16() local
1765 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); in translate_mac16()
1775 tcg_gen_mul_i32(lo, m1, m2); in translate_mac16()