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/linux/drivers/net/wireless/realtek/rtw88/
H A Dfw.h400 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ argument
401 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
402 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ argument
403 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
404 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ argument
405 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
406 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ argument
407 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
416 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ argument
417 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
[all …]
/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-video.c24 u32 value = 0; in medusa_enable_bluefield_output() local
63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output()
64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output()
69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output()
70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output()
72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output()
80 u32 value = 0; in medusa_initialize_ntsc() local
[all …]
/linux/tools/testing/selftests/kvm/include/x86/
H A Devmcs.h268 static inline int evmcs_vmptrst(uint64_t *value) in evmcs_vmptrst() argument
270 *value = current_vp_assist->current_nested_vmcs & in evmcs_vmptrst()
276 static inline int evmcs_vmread(uint64_t encoding, uint64_t *value) in evmcs_vmread() argument
280 *value = current_evmcs->guest_rip; in evmcs_vmread()
283 *value = current_evmcs->guest_rsp; in evmcs_vmread()
286 *value = current_evmcs->guest_rflags; in evmcs_vmread()
289 *value = current_evmcs->host_ia32_pat; in evmcs_vmread()
292 *value = current_evmcs->host_ia32_efer; in evmcs_vmread()
295 *value = current_evmcs->host_cr0; in evmcs_vmread()
298 *value = current_evmcs->host_cr3; in evmcs_vmread()
[all …]
/linux/drivers/phy/tegra/
H A Dxusb-tegra210.c468 u32 value; in tegra210_pex_uphy_enable() local
486 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
487 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_pex_uphy_enable()
489 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_pex_uphy_enable()
491 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
493 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
494 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_pex_uphy_enable()
496 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_pex_uphy_enable()
498 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
500 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
[all …]
H A Dxusb-tegra186.c281 static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset) in ao_writel() argument
283 writel(value, priv->ao_regs + offset); in ao_writel()
337 u32 value; in tegra186_utmi_enable_phy_sleepwalk() local
342 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
343 value &= ~MASTER_ENABLE; in tegra186_utmi_enable_phy_sleepwalk()
344 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
347 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
348 value |= MASTER_CFG_SEL; in tegra186_utmi_enable_phy_sleepwalk()
349 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
352 value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL); in tegra186_utmi_enable_phy_sleepwalk()
[all …]
H A Dxusb-tegra124.c227 u32 value; in tegra124_xusb_padctl_enable() local
234 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
235 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; in tegra124_xusb_padctl_enable()
236 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
240 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
241 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra124_xusb_padctl_enable()
242 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
246 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
247 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; in tegra124_xusb_padctl_enable()
248 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_opp_csc_v.c127 uint32_t value = 0; in program_color_matrix_v() local
131 value, in program_color_matrix_v()
137 value, in program_color_matrix_v()
142 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
145 uint32_t value = 0; in program_color_matrix_v() local
149 value, in program_color_matrix_v()
155 value, in program_color_matrix_v()
160 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
163 uint32_t value = 0; in program_color_matrix_v() local
167 value, in program_color_matrix_v()
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H A Ddce110_opp_regamma_v.c37 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut() local
43 value, in power_on_lut()
49 value, in power_on_lut()
56 value, in power_on_lut()
62 value, in power_on_lut()
68 dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value); in power_on_lut()
71 value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
72 if (get_reg_field_value(value, in power_on_lut()
75 get_reg_field_value(value, in power_on_lut()
86 uint32_t value; in set_bypass_input_gamma() local
[all …]
H A Ddce110_timing_generator.c95 uint32_t value = 0; in dce110_timing_generator_is_in_vertical_blank() local
100 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
101 field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK); in dce110_timing_generator_is_in_vertical_blank()
128 uint32_t value = 0; in dce110_timing_generator_enable_crtc() local
135 value, in dce110_timing_generator_enable_crtc()
140 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); in dce110_timing_generator_enable_crtc()
143 value = 0; in dce110_timing_generator_enable_crtc()
144 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value); in dce110_timing_generator_enable_crtc()
157 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_program_blank_color() local
160 value, in dce110_timing_generator_program_blank_color()
[all …]
H A Ddce110_mem_input_v.c43 uint32_t value = 0; in set_flip_control() local
45 value = dm_read_reg( in set_flip_control()
49 set_reg_field_value(value, 1, in set_flip_control()
56 value); in set_flip_control()
64 uint32_t value = 0; in program_pri_addr_c() local
70 set_reg_field_value(value, temp, in program_pri_addr_c()
77 value); in program_pri_addr_c()
79 value = 0; in program_pri_addr_c()
83 set_reg_field_value(value, temp, in program_pri_addr_c()
90 value); in program_pri_addr_c()
[all …]
H A Ddce110_timing_generator_v.c59 uint32_t value; in dce110_timing_generator_v_enable_crtc() local
61 value = 0; in dce110_timing_generator_v_enable_crtc()
62 set_reg_field_value(value, 0, in dce110_timing_generator_v_enable_crtc()
65 mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
68 value = 0; in dce110_timing_generator_v_enable_crtc()
69 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
71 value = 0; in dce110_timing_generator_v_enable_crtc()
72 set_reg_field_value(value, 1, in dce110_timing_generator_v_enable_crtc()
75 mmCRTCV_MASTER_EN, value); in dce110_timing_generator_v_enable_crtc()
82 uint32_t value; in dce110_timing_generator_v_disable_crtc() local
[all …]
/linux/drivers/video/fbdev/riva/
H A Dnvreg.h34 #define SetBF(mask,value) ((value) << (0?mask)) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
60 #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) argument
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/linux/tools/power/x86/intel-speed-select/
H A Disst-display.c85 char *value) in format_and_print_txt() argument
102 if (header && value) { in format_and_print_txt()
104 fprintf(outf, "%s:%s\n", header, value); in format_and_print_txt()
112 static void format_and_print(FILE *outf, int level, char *header, char *value) in format_and_print() argument
119 format_and_print_txt(outf, level, header, value); in format_and_print()
139 if (value) { in format_and_print()
144 fprintf(outf, "\"%s\"", value); in format_and_print()
222 static char value[1024]; in _isst_pbf_display_information() local
228 snprintf(value, sizeof(value), "%d", in _isst_pbf_display_information()
230 format_and_print(outf, disp_level + 1, header, value); in _isst_pbf_display_information()
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/linux/tools/perf/util/annotate-arch/
H A Dannotate-powerpc.c146 int value; member
168 { .name = "OP_31_XOP_LXSIWZX", .value = 12, },
169 { .name = "OP_31_XOP_LWARX", .value = 20, },
170 { .name = "OP_31_XOP_LDX", .value = 21, },
171 { .name = "OP_31_XOP_LWZX", .value = 23, },
172 { .name = "OP_31_XOP_LDUX", .value = 53, },
173 { .name = "OP_31_XOP_LWZUX", .value = 55, },
174 { .name = "OP_31_XOP_LXSIWAX", .value = 76, },
175 { .name = "OP_31_XOP_LDARX", .value = 84, },
176 { .name = "OP_31_XOP_LBZX", .value = 87, },
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/linux/drivers/gpu/drm/amd/display/include/
H A Dfixed31_32.h58 long long value; member
91 res.value = (long long) arg << FIXED31_32_BITS_PER_FRACTIONAL_PART; in dc_fixpt_from_int()
109 res.value = -arg.value; in dc_fixpt_neg()
120 if (arg.value < 0) in dc_fixpt_abs()
137 return arg1.value < arg2.value; in dc_fixpt_lt()
146 return arg1.value <= arg2.value; in dc_fixpt_le()
155 return arg1.value == arg2.value; in dc_fixpt_eq()
164 if (arg1.value <= arg2.value) in dc_fixpt_min()
176 if (arg1.value <= arg2.value) in dc_fixpt_max()
212 ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) || in dc_fixpt_shl()
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/linux/tools/testing/selftests/bpf/test_kmods/
H A Dbpf_testmod.h30 s64 value; member
57 int (*tramp_1)(int value);
58 int (*tramp_2)(int value);
59 int (*tramp_3)(int value);
60 int (*tramp_4)(int value);
61 int (*tramp_5)(int value);
62 int (*tramp_6)(int value);
63 int (*tramp_7)(int value);
64 int (*tramp_8)(int value);
65 int (*tramp_9)(int value);
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c1343 if (ratio.value < dc_fixpt_one.value) in get_filter_3tap_16p()
1345 else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) in get_filter_3tap_16p()
1347 else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) in get_filter_3tap_16p()
1355 if (ratio.value < dc_fixpt_one.value) in get_filter_3tap_64p()
1357 else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) in get_filter_3tap_64p()
1359 else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) in get_filter_3tap_64p()
1367 if (ratio.value < dc_fixpt_one.value) in get_filter_4tap_16p()
1369 else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) in get_filter_4tap_16p()
1371 else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) in get_filter_4tap_16p()
1379 if (ratio.value < dc_fixpt_one.value) in get_filter_4tap_64p()
[all …]
/linux/drivers/gpu/drm/i915/
H A Di915_getparam.c25 int value = 0; in i915_getparam_ioctl() local
35 value = pdev->device; in i915_getparam_ioctl()
38 value = pdev->revision; in i915_getparam_ioctl()
41 value = to_gt(i915)->ggtt->num_fences; in i915_getparam_ioctl()
44 value = intel_overlay_available(display); in i915_getparam_ioctl()
47 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
51 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
55 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
59 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
63 value = HAS_LLC(i915); in i915_getparam_ioctl()
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_vlan.c168 u32 value; in vlan_update_hash() local
172 value = readl(ioaddr + VLAN_TAG); in vlan_update_hash()
175 value |= VLAN_VTHM | VLAN_ETV; in vlan_update_hash()
177 value |= VLAN_EDVLP; in vlan_update_hash()
178 value |= VLAN_ESVL; in vlan_update_hash()
179 value |= VLAN_DOVLTC; in vlan_update_hash()
181 value &= ~VLAN_EDVLP; in vlan_update_hash()
182 value &= ~VLAN_ESVL; in vlan_update_hash()
183 value &= ~VLAN_DOVLTC; in vlan_update_hash()
186 writel(value, ioaddr + VLAN_TAG); in vlan_update_hash()
[all …]
H A Ddwmac4_core.c40 u32 value; in dwmac4_core_init() local
42 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_core_init()
43 writel(value | GMAC_CORE_INIT, ioaddr + GMAC_CONFIG); in dwmac4_core_init()
61 u32 value; in dwmac4_irq_modify() local
64 value = readl(int_mask) & ~disable; in dwmac4_irq_modify()
65 value |= enable; in dwmac4_irq_modify()
66 writel(value, int_mask); in dwmac4_irq_modify()
82 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0); in dwmac4_rx_queue_enable() local
84 value &= GMAC_RX_QUEUE_CLEAR(queue); in dwmac4_rx_queue_enable()
86 value |= GMAC_RX_AV_QUEUE_ENABLE(queue); in dwmac4_rx_queue_enable()
[all …]
/linux/drivers/net/wwan/t7xx/
H A Dt7xx_dpmaif.c37 u32 value, ul_intr_enable, dl_intr_enable; in t7xx_dpmaif_init_intr() local
50 value, (value & ul_intr_enable) != ul_intr_enable, 0, in t7xx_dpmaif_init_intr()
65 value, (value & ul_intr_enable) != ul_intr_enable, 0, in t7xx_dpmaif_init_intr()
74 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
75 value |= DPMAIF_DL_INT_Q2APTOP | DPMAIF_DL_INT_Q2TOQ1; in t7xx_dpmaif_init_intr()
76 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
85 u32 value, ul_int_que_done; in t7xx_dpmaif_mask_ulq_intr() local
94 value, (value & ul_int_que_done) == ul_int_que_done, 0, in t7xx_dpmaif_mask_ulq_intr()
99 value); in t7xx_dpmaif_mask_ulq_intr()
105 u32 value, ul_int_que_done; in t7xx_dpmaif_unmask_ulq_intr() local
[all …]
/linux/arch/mips/include/asm/
H A Dunaligned-emul.h8 #define _LoadHW(addr, value, res, type) \ argument
26 : "=&r" (value), "=r" (res) \
31 #define _LoadW(addr, value, res, type) \ argument
47 : "=&r" (value), "=r" (res) \
53 #define _LoadW(addr, value, res, type) \ argument
82 : "=&r" (value), "=r" (res) \
88 #define _LoadHWU(addr, value, res, type) \ argument
108 : "=&r" (value), "=r" (res) \
113 #define _LoadWU(addr, value, res, type) \ argument
131 : "=&r" (value), "=r" (res) \
[all …]
/linux/drivers/gpu/drm/tegra/
H A Dsor.c489 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
491 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
493 return value; in tegra_sor_readl()
496 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
499 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
500 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
547 u32 value; in tegra_clk_sor_pad_set_parent() local
549 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
550 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
554 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
[all …]
/linux/drivers/net/ethernet/qualcomm/ppe/
H A Dppe_regs.h108 #define PPE_SERVICE_SET_BYPASS_BITMAP(tbl_cfg, value) \ argument
109 FIELD_MODIFY(PPE_SERVICE_W0_BYPASS_BITMAP, tbl_cfg, value)
110 #define PPE_SERVICE_SET_RX_CNT_EN(tbl_cfg, value) \ argument
111 FIELD_MODIFY(PPE_SERVICE_W1_RX_CNT_EN, (tbl_cfg) + 0x1, value)
139 #define PPE_EG_SERVICE_SET_UPDATE_ACTION(tbl_cfg, value) \ argument
140 FIELD_MODIFY(PPE_EG_SERVICE_W0_UPDATE_ACTION, tbl_cfg, value)
141 #define PPE_EG_SERVICE_SET_NEXT_SERVCODE(tbl_cfg, value) \ argument
142 FIELD_MODIFY(PPE_EG_SERVICE_W1_NEXT_SERVCODE, (tbl_cfg) + 0x1, value)
143 #define PPE_EG_SERVICE_SET_HW_SERVICE(tbl_cfg, value) \ argument
144 FIELD_MODIFY(PPE_EG_SERVICE_W1_HW_SERVICE, (tbl_cfg) + 0x1, value)
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h62 int64_t value:63; member
72 int32_t value:31; member
82 int16_t value:15; member
92 int8_t value:7; member
153 int64_t value) in __cvmx_fau_atomic_address() argument
156 cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | in __cvmx_fau_atomic_address()
171 int64_t value) in cvmx_fau_fetch_and_add64() argument
173 return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add64()
186 int32_t value) in cvmx_fau_fetch_and_add32() argument
189 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add32()
[all …]

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