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Searched refs:train_set (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/hisilicon/hibmc/dp/
H A Ddp_link.c110 u8 *train_set = dp->link.train_set; in hibmc_dp_link_training_cr_pre() local
123 train_set[i] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; in hibmc_dp_link_training_cr_pre()
125 ret = hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set); in hibmc_dp_link_training_cr_pre()
129 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes); in hibmc_dp_link_training_cr_pre()
141 u8 train_set[HIBMC_DP_LANE_NUM_MAX] = {0}; in hibmc_dp_link_get_adjust_train() local
145 train_set[lane] = drm_dp_get_adjust_request_voltage(lane_status, lane) | in hibmc_dp_link_get_adjust_train()
148 if (memcmp(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX)) { in hibmc_dp_link_get_adjust_train()
149 memcpy(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX); in hibmc_dp_link_get_adjust_train()
235 ret = hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set); in hibmc_dp_link_training_cr()
239 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set, in hibmc_dp_link_training_cr()
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H A Ddp_serdes.c11 int hibmc_dp_serdes_set_tx_cfg(struct hibmc_dp_dev *dp, u8 train_set[HIBMC_DP_LANE_NUM_MAX]) in hibmc_dp_serdes_set_tx_cfg()
22 cfg[i] = serdes_tx_cfg[FIELD_GET(DP_TRAIN_VOLTAGE_SWING_MASK, train_set[i])] in hibmc_dp_serdes_set_tx_cfg()
23 [FIELD_GET(DP_TRAIN_PRE_EMPHASIS_MASK, train_set[i])]; in hibmc_dp_serdes_set_tx_cfg()
/linux/drivers/gpu/drm/i915/display/
H A Dg4x_dp.c830 u8 train_set = intel_dp->train_set[0]; in vlv_set_signal_levels() local
832 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_set_signal_levels()
835 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
858 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
877 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
892 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
916 u8 train_set = intel_dp->train_set[0]; in chv_set_signal_levels() local
918 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_set_signal_levels()
920 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_set_signal_levels()
943 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_set_signal_levels()
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H A Dintel_dp_test.c329 intel_dp->train_set, crtc_state->lane_count); in intel_dp_process_phy_request()
700 intel_dp->train_set[0]); in i915_displayport_test_data_show()
H A Dintel_display_types.h1858 u8 train_set[4]; member
H A Dintel_dp.c3489 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_set_link_params()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_dp.c205 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train()
237 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
496 u8 train_set[4]; member
508 0, dp_info->train_set[0]); /* sets all lanes at once */ in amdgpu_atombios_dp_update_vs_emph()
512 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
606 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
630 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in amdgpu_atombios_dp_link_train_cr()
638 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in amdgpu_atombios_dp_link_train_cr()
647 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in amdgpu_atombios_dp_link_train_cr()
651 dp_info->train_set); in amdgpu_atombios_dp_link_train_cr()
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/linux/drivers/gpu/drm/radeon/
H A Datombios_dp.c254 u8 train_set[4]) in dp_get_adjust_train()
286 train_set[lane] = v | p; in dp_get_adjust_train()
541 u8 train_set[4]; member
553 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
557 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
668 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
692 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
700 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
709 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
712 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()
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/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c332 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
407 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
697 u8 *train_set = dp->train_set; in zynqmp_dp_adjust_train() local
711 train_set[i] = voltage | preemphasis; in zynqmp_dp_adjust_train()
726 static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp, u8 *train_set) in zynqmp_dp_update_vs_emph() argument
731 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, in zynqmp_dp_update_vs_emph()
739 u8 train = train_set[i]; in zynqmp_dp_update_vs_emph()
783 ret = zynqmp_dp_update_vs_emph(dp, dp->train_set); in zynqmp_dp_link_train_cr()
797 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) in zynqmp_dp_link_train_cr()
802 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) in zynqmp_dp_link_train_cr()
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/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c268 uint8_t train_set[4]; member
1297 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train()
1386 intel_dp->train_set, in cdv_intel_dplink_set_level()
1391 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level()
1491 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train()
1502 intel_dp->train_set[0], in cdv_intel_dp_start_link_train()
1509 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train()
1530 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train()
1536 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in cdv_intel_dp_start_link_train()
1542 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in cdv_intel_dp_start_link_train()
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/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-dp.c557 struct dw_dp_link_train_set *train_set = &link->train.adjust; in dw_dp_link_train_update_vs_emph() local
564 vs = train_set->voltage_swing; in dw_dp_link_train_update_vs_emph()
565 pe = train_set->pre_emphasis; in dw_dp_link_train_update_vs_emph()
583 if (train_set->voltage_max_reached[i]) in dw_dp_link_train_update_vs_emph()
585 if (train_set->pre_max_reached[i]) in dw_dp_link_train_update_vs_emph()