Searched refs:stvec (Results 1 – 4 of 4) sorted by relevance
78 unsigned long stvec; member
353 vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(stvec), (unsigned long)guest_unexp_trap); in vm_arch_vcpu_add()447 vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(stvec), (unsigned long)&exception_vectors); in vcpu_init_vector_tables()
337 case KVM_REG_RISCV_CSR_REG(stvec): in general_csr_id_to_str()338 return RISCV_CSR_GENERAL(stvec); in general_csr_id_to_str()860 … KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stvec),
2844 0x80x0 0000 0300 0002 stvec Supervisor trap vector base