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Searched refs:status_base (Results 1 – 25 of 94) sorted by relevance

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/linux/drivers/mfd/
H A Dsec-irq.c251 .status_base = S2MPG10_COMMON_INT,
261 .status_base = S2MPG10_PMIC_INT1,
270 .status_base = S2MPG11_COMMON_INT,
280 .status_base = S2MPG11_PMIC_INT1,
292 .status_base = S2MPS11_REG_INT1,
301 .status_base = S2MPS14_REG_INT1, \
325 .status_base = S2MPU02_REG_INT1,
335 .status_base = S2MPU05_REG_INT1,
345 .status_base = S5M8767_REG_INT1,
H A Dmax77541.c26 .status_base = MAX77541_REG_INT_SRC,
44 .status_base = MAX77541_REG_TOPSYS_INT,
60 .status_base = MAX77541_REG_BUCK_INT,
76 .status_base = MAX77541_REG_ADC_INT,
H A Dintel_soc_pmic_bxtwc.c153 .status_base = BXTWC_IRQLVL1,
163 .status_base = BXTWC_PWRBTNIRQ,
173 .status_base = BXTWC_TMUIRQ,
183 .status_base = BXTWC_BCUIRQ,
193 .status_base = BXTWC_ADCIRQ,
203 .status_base = BXTWC_CHGR0IRQ,
213 .status_base = BXTWC_CRITIRQ,
H A Dpf1550.c35 .status_base = PF1550_PMIC_REG_INT_CATEGORY,
58 .status_base = PF1550_PMIC_REG_SW_INT_STAT0,
93 .status_base = PF1550_PMIC_REG_ONKEY_INT_STAT0,
122 .status_base = PF1550_CHARG_REG_CHG_INT,
H A Dmax77693.c67 .status_base = MAX77693_LED_REG_FLASH_INT,
82 .status_base = MAX77693_PMIC_REG_TOPSYS_INT,
99 .status_base = MAX77693_CHG_REG_CHG_INT,
135 .status_base = MAX77693_MUIC_REG_INT1,
H A Drk8xx-core.c593 .status_base = RK801_INT_STS0_REG,
604 .status_base = RK805_INT_STS_REG,
617 .status_base = RK806_INT_STS0,
628 .status_base = RK808_INT_STS_REG1,
640 .status_base = RK816_INT_STS_REG1,
652 .status_base = RK817_INT_STS_REG0,
664 .status_base = RK818_INT_STS_REG1,
H A Daxp20x.c806 .status_base = AXP152_IRQ1_STATE,
831 .status_base = AXP192_IRQ1_STATE,
843 .status_base = AXP20X_IRQ1_STATE,
855 .status_base = AXP20X_IRQ1_STATE,
866 .status_base = AXP20X_IRQ1_STATE,
878 .status_base = AXP313A_IRQ_STATE,
889 .status_base = AXP717_IRQ0_STATE,
900 .status_base = AXP20X_IRQ1_STATE,
911 .status_base = AXP20X_IRQ1_STATE,
922 .status_base = AXP20X_IRQ1_STATE,
[all …]
H A Dmax8907.c130 .status_base = MAX8907_REG_CHG_IRQ1,
154 .status_base = MAX8907_REG_ON_OFF_IRQ1,
169 .status_base = MAX8907_REG_RTC_IRQ,
H A Dmotorola-cpcap.c96 .status_base = CPCAP_REG_MI1,
105 .status_base = CPCAP_REG_MI2,
114 .status_base = CPCAP_REG_INT1,
H A Dmax77759.c266 .status_base = MAX77759_PMIC_REG_INTSRC,
282 .status_base = MAX77759_MAXQ_REG_UIC_INT1,
292 .status_base = MAX77759_PMIC_REG_TOPSYS_INT,
303 .status_base = MAX77759_CHGR_REG_CHG_INT,
H A Dda9063-irq.c93 .status_base = DA9063_REG_EVENT_A,
165 .status_base = DA9063_REG_EVENT_A,
H A Dmax14577.c213 .status_base = MAX14577_REG_INT1,
242 .status_base = MAX14577_REG_INT1,
256 .status_base = MAX77836_PMIC_REG_TOPSYS_INT,
H A Dmax77686.c131 .status_base = MAX77686_REG_INT1,
140 .status_base = MAX77802_REG_INT1,
H A Datc260x-core.c101 .status_base = ATC2603C_INTS_PD,
110 .status_base = ATC2609A_INTS_PD,
H A Dbd9571mwv.c98 .status_base = BD9571MWV_INT_INTREQ,
164 .status_base = BD9571MWV_INT_INTREQ,
H A Dretu-mfd.c79 .status_base = RETU_REG_IDR,
115 .status_base = RETU_REG_IDR,
H A Drohm-bd96801.c514 .status_base = BD96801_REG_INT_SYS_ERRB1,
530 .status_base = BD96801_REG_INT_SYS_ERRB1,
546 .status_base = BD96801_REG_INT_SYS_INTB,
561 .status_base = BD96801_REG_INT_SYS_INTB,
H A Drt5120.c61 .status_base = RT5120_REG_INTSTAT,
H A Dtps65910.c206 .status_base = TPS65910_INT_STS,
217 .status_base = TPS65910_INT_STS,
H A Dtps65219.c417 .status_base = TPS65214_REG_INT_LDO_1_2,
431 .status_base = TPS65215_REG_INT_LDO_2,
445 .status_base = TPS65219_REG_INT_LDO_3_4,
/linux/drivers/clk/bcm/
H A Dclk-iproc-pll.c63 void __iomem *status_base; member
153 u32 val = readl(pll->status_base + ctrl->status.offset); in pll_wait_for_lock()
171 (base == pll->status_base || base == pll->control_base))) in iproc_pll_write()
285 val = readl(pll->status_base + ctrl->status.offset); in pll_fractional_change_only()
462 val = readl(pll->status_base + ctrl->status.offset); in iproc_pll_recalc_rate()
765 pll->status_base = of_iomap(node, 2); in iproc_pll_clk_setup()
766 if (!pll->status_base) in iproc_pll_clk_setup()
769 pll->status_base = pll->control_base; in iproc_pll_clk_setup()
842 if (pll->status_base != pll->control_base) in iproc_pll_clk_setup()
843 iounmap(pll->status_base); in iproc_pll_clk_setup()
/linux/drivers/pci/controller/cadence/
H A Dpci-sky1.c47 void __iomem *status_base; member
81 pcie->status_base = base; in sky1_pcie_resource_get()
/linux/drivers/base/regmap/
H A Dregmap-irq.c100 reg = d->get_irq_reg(d, d->chip->status_base, i); in regmap_irq_sync_unlock()
318 reg = data->get_irq_reg(data, chip->status_base, b); in read_sub_irq_data()
330 ret = regmap_read(map, chip->status_base + offset, in read_sub_irq_data()
403 ret = regmap_bulk_read(map, chip->status_base, in read_irq_data()
431 data->chip->status_base, i); in read_irq_data()
860 reg = d->get_irq_reg(d, d->chip->status_base, i); in regmap_add_irq_chip_fwnode()
/linux/drivers/dma/
H A Dfsl-qdma.c219 void __iomem *status_base; member
745 void __iomem *status = fsl_qdma->status_base; in fsl_qdma_error_handler()
876 void __iomem *status = fsl_qdma->status_base; in fsl_qdma_reg_init()
1192 fsl_qdma->status_base = devm_platform_ioremap_resource(pdev, 1); in fsl_qdma_probe()
1193 if (IS_ERR(fsl_qdma->status_base)) in fsl_qdma_probe()
1194 return PTR_ERR(fsl_qdma->status_base); in fsl_qdma_probe()
/linux/drivers/irqchip/
H A Dirq-sl28cpld.c67 irqchip->chip.status_base = base + INTC_IP; in sl28cpld_intc_probe()

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