Searched refs:stage3 (Results 1 – 9 of 9) sorted by relevance
207 if (!display_cfg->stage3.performed) { in expand_implict_subvp()217 if (display_cfg->stage3.stream_svp_meta[stream_index].valid) { in expand_implict_subvp()220 main_stream, &display_cfg->stage3.stream_svp_meta[stream_index]); in expand_implict_subvp()235 if (display_cfg->stage3.stream_svp_meta[main_plane->stream_index].valid) { in expand_implict_subvp()276 if (display_cfg->stage3.performed && display_cfg->stage3.success) { in pack_mode_programming_params_with_implicit_subvp()277 programming->fams2_required = display_cfg->stage3.fams2_required; in pack_mode_programming_params_with_implicit_subvp()321 if (display_cfg->stage3.performed && display_cfg->stage3.success) { in pack_mode_programming_params_with_implicit_subvp()322 …programming->plane_programming[plane_index].uclk_pstate_support_method = display_cfg->stage3.pstat… in pack_mode_programming_params_with_implicit_subvp()
627 if (!display_cfg->stage3.performed) { in dml2_core_utils_expand_implict_subvp()637 if (display_cfg->stage3.stream_svp_meta[stream_index].valid) { in dml2_core_utils_expand_implict_subvp()640 main_stream, &display_cfg->stage3.stream_svp_meta[stream_index]); in dml2_core_utils_expand_implict_subvp()655 if (display_cfg->stage3.stream_svp_meta[main_plane->stream_index].valid) { in dml2_core_utils_expand_implict_subvp()
12775 fams2_global_config->features.bits.enable = display_cfg->stage3.fams2_required; in dml2_core_calcs_get_global_fams2_programming()12799 …const struct dml2_pstate_meta *stream_pstate_meta = &display_cfg->stage3.stream_pstate_meta[plane_… in dml2_core_calcs_get_stream_fams2_programming()
798 else if (in_out->base_display_config->stage3.stream_svp_meta[i].valid && in pmo_dcn4_fams2_init_for_vmin()1859 struct dml2_optimization_stage3_state *state = &in_out->base_display_config->stage3; in pmo_dcn4_fams2_init_for_pstate_support()1871 …in_out->base_display_config->stage3.min_clk_index_for_latency = in_out->base_display_config->stage… in pmo_dcn4_fams2_init_for_pstate_support()1964 display_config->stage3.stream_svp_meta[stream_index].valid = false; in reset_display_configuration()1979 display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_na; in reset_display_configuration()1996 display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_drr; in setup_planes_for_drr_by_mask()2013 display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_svp; in setup_planes_for_svp_by_mask()2018 memcpy(&display_config->stage3.stream_svp_meta[stream_index], in setup_planes_for_svp_by_mask()2036 display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_svp_drr; in setup_planes_for_svp_drr_by_mask()2041 memcpy(&display_config->stage3.stream_svp_meta[stream_index], in setup_planes_for_svp_drr_by_mask()[all …]
312 else if (in_out->base_display_config->stage3.stream_svp_meta[i].valid && in pmo_dcn3_init_for_vmin()528 struct dml2_optimization_stage3_state *state = &in_out->base_display_config->stage3; in pmo_dcn3_init_for_pstate_support()697 …in_out->optimized_display_config->stage3.min_clk_index_for_latency = pmo->scratch.pmo_dcn3.cur_lat… in pmo_dcn3_optimize_for_pstate_support()
150 stage3: in process_fetch_insn_bottom()216 goto stage3; in process_fetch_insn_bottom()
39 if (in_out->display_cfg->stage3.success) in get_minimum_clocks_for_latency()40 min_clock_index_for_latency = in_out->display_cfg->stage3.min_clk_index_for_latency; in get_minimum_clocks_for_latency()715 if (in_out->display_cfg->stage3.success) in dpmm_dcn4_map_mode_to_soc_dpm()
253 if (l->next_candidate_display_cfg.stage3.performed) in dml2_top_optimization_perform_optimization_phase()254 …l->mode_support_params.min_clk_index = l->next_candidate_display_cfg.stage3.min_clk_index_for_late… in dml2_top_optimization_perform_optimization_phase()928 l->base_display_config_with_meta.stage3.success = true; in dml2_top_soc15_build_mode_programming()
369 struct dml2_optimization_stage3_state stage3; member