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Searched refs:rvu_read64 (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_cpt.c35 reg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_STS(e)); \
55 reg = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_CONSTANTS1); in cpt_max_engines_get()
90 reg = rvu_read64(rvu, blkaddr, CPT_AF_FLTX_INT(vec)); in cpt_af_flt_intr_handler()
106 grp = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng)) & 0xFF; in cpt_af_flt_intr_handler()
109 val = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL(eng)); in cpt_af_flt_intr_handler()
117 val = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_STS(eng)); in cpt_af_flt_intr_handler()
150 reg = rvu_read64(rvu, blkaddr, CPT_AF_RVU_INT); in rvu_cpt_af_rvu_intr_handler()
164 reg = rvu_read64(rvu, blkaddr, CPT_AF_RAS_INT); in rvu_cpt_af_ras_intr_handler()
228 offs = rvu_read64(rvu, blkaddr, CPT_PRIV_AF_INT_CFG) & 0x7FF; in cpt_unregister_interrupts()
329 offs = rvu_read64(rvu, blkaddr, CPT_PRIV_AF_INT_CFG) & 0x7FF; in cpt_register_interrupts()
[all …]
H A Drvu_debugfs.c573 tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE); in rvu_dbg_lmtst_map_table_display()
574 val = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG); in rvu_dbg_lmtst_map_table_display()
1458 req = rvu_read64(rvu, blk_addr, NDC_AF_PORTX_RTX_RWX_REQ_PC in ndc_cache_stats()
1460 lat = rvu_read64(rvu, blk_addr, NDC_AF_PORTX_RTX_RWX_LAT_PC in ndc_cache_stats()
1462 out_req = rvu_read64(rvu, blk_addr, in ndc_cache_stats()
1465 cant_alloc = rvu_read64(rvu, blk_addr, in ndc_cache_stats()
1511 ndc_af_const = rvu_read64(rvu, blk_addr, NDC_AF_CONST); in ndc_blk_hits_miss_stats()
1516 (u64)rvu_read64(rvu, blk_addr, in ndc_blk_hits_miss_stats()
1519 (u64)rvu_read64(rvu, blk_addr, in ndc_blk_hits_miss_stats()
1672 cfg = rvu_read64(rvu, blkaddr, NIX_AF_MDQX_PARENT(schq)); in print_tm_tree()
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H A Drvu_cn10k.c30 tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE); in lmtst_map_table_ops()
31 cfg = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG); in lmtst_map_table_ops()
58 rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CTL); in lmtst_map_table_ops()
96 val = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_RSP_STS); in rvu_get_lmtaddr()
105 pa = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TLN_FLIT0) >> 18; in rvu_get_lmtaddr()
308 nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST); in rvu_set_channels_base()
309 nix_const1 = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); in rvu_set_channels_base()
453 u64 nix_const1 = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); in __rvu_nix_set_channels()
454 u64 nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST); in __rvu_nix_set_channels()
468 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link)); in __rvu_nix_set_channels()
[all …]
H A Drvu_npa.c26 reg = rvu_read64(rvu, block->addr, NPA_AF_AQ_STATUS); in npa_aq_enqueue_wait()
363 ctx_cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST1); in rvu_mbox_handler_npa_lf_alloc()
389 cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST); in rvu_mbox_handler_npa_lf_alloc()
398 cfg = rvu_read64(rvu, blkaddr, NPA_AF_LFX_AURAS_CFG(npalf)); in rvu_mbox_handler_npa_lf_alloc()
424 cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST); in rvu_mbox_handler_npa_lf_alloc()
429 cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL); in rvu_mbox_handler_npa_lf_alloc()
475 cfg = rvu_read64(rvu, block->addr, NPA_AF_NDC_CFG); in npa_aq_ndc_config()
490 cfg = rvu_read64(rvu, block->addr, NPA_AF_GEN_CFG); in npa_aq_init()
503 cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL); in npa_aq_init()
584 reg = rvu_read64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL); in rvu_ndc_fix_locked_cacheline()
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H A Drvu.c306 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); in rvu_get_blkaddr()
314 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); in rvu_get_blkaddr()
322 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); in rvu_get_blkaddr()
330 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); in rvu_get_blkaddr()
408 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); in rvu_get_pf_numvfs()
424 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); in rvu_get_hwvf()
452 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); in is_pf_func_valid()
555 cfg = rvu_read64(rvu, block->addr, in rvu_scan_block()
610 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); in rvu_setup_msix_resources()
619 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); in rvu_setup_msix_resources()
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H A Drvu_nix.c513 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); in nix_setup_bpids()
614 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v)); in nix_bp_disable()
768 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan_v)); in nix_bp_enable()
860 cfg = (rvu_read64(rvu, blkaddr, NIX_AF_CONST1) >> 48) & 0xFF; in nix_setup_lso()
864 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LSO_CFG); in nix_setup_lso()
978 reg = rvu_read64(rvu, block->addr, NIX_AF_AQ_STATUS); in nix_aq_enqueue_wait()
1090 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf)); in rvu_nix_blk_aq_enq_inst()
1096 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG); in rvu_nix_blk_aq_enq_inst()
1565 ctx_cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST3); in rvu_mbox_handler_nix_lf_alloc()
1625 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); in rvu_mbox_handler_nix_lf_alloc()
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H A Drvu_devlink.c70 intr = rvu_read64(rvu, blkaddr, NIX_AF_RVU_INT); in rvu_nix_af_rvu_intr_handler()
105 intr = rvu_read64(rvu, blkaddr, NIX_AF_GEN_INT); in rvu_nix_af_rvu_gen_handler()
140 intr = rvu_read64(rvu, blkaddr, NIX_AF_ERR_INT); in rvu_nix_af_rvu_err_handler()
175 intr = rvu_read64(rvu, blkaddr, NIX_AF_ERR_INT); in rvu_nix_af_rvu_ras_handler()
195 offs = rvu_read64(rvu, blkaddr, NIX_PRIV_AF_INT_CFG) & 0x3ff; in rvu_nix_unregister_interrupts()
227 base = rvu_read64(rvu, blkaddr, NIX_PRIV_AF_INT_CFG) & 0x3ff; in rvu_nix_register_interrupts()
625 intr = rvu_read64(rvu, blkaddr, NPA_AF_RVU_INT); in rvu_npa_af_rvu_intr_handler()
660 intr = rvu_read64(rvu, blkaddr, NPA_AF_GEN_INT); in rvu_npa_af_gen_intr_handler()
694 intr = rvu_read64(rvu, blkaddr, NPA_AF_ERR_INT); in rvu_npa_af_err_intr_handler()
729 intr = rvu_read64(rvu, blkaddr, NPA_AF_RAS); in rvu_npa_af_ras_intr_handler()
[all …]
H A Drvu_npc.c111 val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind)); in npc_config_ts_kpuaction()
192 cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank)); in is_mcam_entry_enabled()
384 return rvu_read64(rvu, blkaddr, in npc_get_default_entry_action()
518 cam1 = rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
520 cam0 = rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
524 cam1 = rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
526 cam0 = rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
531 entry->action = rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
534 rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
536 *intf = rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
[all …]
H A Drvu_npc_hash.h35 rvu_read64(rvu, blkaddr, NPC_AF_INTFX_HASHX_RESULT_CTRL(intf, ld))
38 rvu_read64(rvu, blkaddr, NPC_AF_INTFX_HASHX_MASKX(intf, ld, mask_idx))
H A Drvu_npc_hash.c109 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld)); in npc_update_use_hash()
247 cfg = rvu_read64(rvu, blkaddr, in npc_program_mkex_hash()
300 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_HASHX_CFG(intf, hash_idx)); in npc_update_field_hash()
373 secret_key[0] = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_SECRET_KEY0(intf)); in rvu_mbox_handler_npc_get_field_hash_info()
374 secret_key[1] = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_SECRET_KEY1(intf)); in rvu_mbox_handler_npc_get_field_hash_info()
375 secret_key[2] = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_SECRET_KEY2(intf)); in rvu_mbox_handler_npc_get_field_hash_info()
1887 npc_const3 = rvu_read64(rvu, blkaddr, NPC_AF_CONST3); in rvu_npc_exact_init()
1892 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX)); in rvu_npc_exact_init()
H A Drvu.h678 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) in rvu_read64() function
699 rvu_read64(rvu, block, offset); in rvu_bar2_sel_write64()
814 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3); in is_rvu_npc_hash_extract_en()
824 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); in rvu_nix_chan_cgx()
838 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); in rvu_nix_chan_lbk()
H A Drvu_sdp.c119 rsp->num_chan = rvu_read64(rvu, blkaddr, NIX_AF_CONST1) & 0xFFFUL; in rvu_mbox_handler_get_sdp_chan_info()
H A Drvu_rep.c142 rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_STATX(nixlf, reg))
145 rvu_read64(rvu, blkaddr, NIX_AF_LFX_TX_STATX(nixlf, reg))
H A Drvu_npc_fs.c218 cfg = rvu_read64(rvu, blkaddr, in npc_check_overlap()
645 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf)); in npc_scan_kex()
667 cfg = rvu_read64(rvu, blkaddr, in npc_scan_kex()
1578 rsp->cntr_val = rvu_read64(rvu, blkaddr, in rvu_mbox_handler_npc_delete_flow()
H A Drvu_cgx.c1116 *stat += rvu_read64(rvu, blkaddr, in rvu_cgx_nix_cuml_stats()
1119 *stat += rvu_read64(rvu, blkaddr, in rvu_cgx_nix_cuml_stats()
/linux/drivers/net/ethernet/marvell/octeontx2/af/cn20k/
H A Dmbox_init.c109 intr = rvu_read64(rvu, BLKADDR_RVUM, rvu_irq_data->intr_status); in cn20k_mbox_pf_common_intr_handler()
400 ctx_cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST3); in rvu_alloc_cint_qint_mem()
402 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); in rvu_alloc_cint_qint_mem()
413 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); in rvu_alloc_cint_qint_mem()