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Searched refs:reg_off (Results 1 – 25 of 92) sorted by relevance

1234

/linux/tools/lib/bpf/
H A Dusdt.c209 short reg_off; member
1246 #define reg_off(reg64, reg32) offsetof(struct pt_regs, reg64) in calc_pt_regs_off() macro
1248 #define reg_off(reg64, reg32) offsetof(struct pt_regs, reg32) in calc_pt_regs_off()
1250 { {"rip", "eip", "", ""}, reg_off(rip, eip) }, in calc_pt_regs_off()
1251 { {"rax", "eax", "ax", "al"}, reg_off(rax, eax) }, in calc_pt_regs_off()
1252 { {"rbx", "ebx", "bx", "bl"}, reg_off(rbx, ebx) }, in calc_pt_regs_off()
1253 { {"rcx", "ecx", "cx", "cl"}, reg_off(rcx, ecx) }, in calc_pt_regs_off()
1254 { {"rdx", "edx", "dx", "dl"}, reg_off(rdx, edx) }, in calc_pt_regs_off()
1255 { {"rsi", "esi", "si", "sil"}, reg_off(rsi, esi) }, in calc_pt_regs_off()
1256 { {"rdi", "edi", "di", "dil"}, reg_off(rd in calc_pt_regs_off()
1287 int len, reg_off; parse_usdt_arg() local
1388 int len, reg_off; parse_usdt_arg() local
1482 int len, reg_off; parse_usdt_arg() local
1553 int len, reg_off; parse_usdt_arg() local
[all...]
/linux/drivers/mmc/host/
H A Dcavium.h37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off)
41 #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
44 #define MIO_EMM_INT(x) (0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
59 int reg_off; global() member
[all...]
/linux/drivers/clk/meson/
H A Ds4-pll.c57 .reg_off = ANACTRL_FIXPLL_CTRL0,
62 .reg_off = ANACTRL_FIXPLL_CTRL0,
67 .reg_off = ANACTRL_FIXPLL_CTRL1,
72 .reg_off = ANACTRL_FIXPLL_CTRL0,
77 .reg_off = ANACTRL_FIXPLL_CTRL0,
82 .reg_off = ANACTRL_FIXPLL_CTRL0,
296 .reg_off = ANACTRL_GP0PLL_CTRL0,
301 .reg_off = ANACTRL_GP0PLL_CTRL0,
306 .reg_off = ANACTRL_GP0PLL_CTRL0,
311 .reg_off
[all...]
H A Da1-pll.c32 .reg_off = ANACTRL_FIXPLL_CTRL0,
37 .reg_off = ANACTRL_FIXPLL_CTRL0,
42 .reg_off = ANACTRL_FIXPLL_CTRL0,
47 .reg_off = ANACTRL_FIXPLL_CTRL1,
52 .reg_off = ANACTRL_FIXPLL_STS,
57 .reg_off = ANACTRL_FIXPLL_CTRL0,
103 .reg_off = ANACTRL_HIFIPLL_CTRL0,
108 .reg_off = ANACTRL_HIFIPLL_CTRL0,
113 .reg_off = ANACTRL_HIFIPLL_CTRL0,
118 .reg_off
[all...]
H A Dc3-pll.c249 .reg_off = ANACTRL_GP0PLL_CTRL0,
254 .reg_off = ANACTRL_GP0PLL_CTRL0,
259 .reg_off = ANACTRL_GP0PLL_CTRL1,
264 .reg_off = ANACTRL_GP0PLL_CTRL0,
269 .reg_off = ANACTRL_GP0PLL_CTRL0,
274 .reg_off = ANACTRL_GP0PLL_CTRL0,
332 .reg_off = ANACTRL_HIFIPLL_CTRL0,
337 .reg_off = ANACTRL_HIFIPLL_CTRL0,
342 .reg_off = ANACTRL_HIFIPLL_CTRL1,
347 .reg_off
[all...]
H A Dmeson8-ddr.c28 .reg_off = AM_DDR_PLL_CNTL,
33 .reg_off = AM_DDR_PLL_CNTL,
38 .reg_off = AM_DDR_PLL_CNTL,
43 .reg_off = AM_DDR_PLL_CNTL,
48 .reg_off = AM_DDR_PLL_CNTL,
H A Dg12a-aoclk.c124 .reg_off = AO_RTC_ALT_CLK_CNTL0,
129 .reg_off = AO_RTC_ALT_CLK_CNTL0,
134 .reg_off = AO_RTC_ALT_CLK_CNTL1,
139 .reg_off = AO_RTC_ALT_CLK_CNTL1,
144 .reg_off = AO_RTC_ALT_CLK_CNTL0,
215 .reg_off = AO_CEC_CLK_CNTL_REG0,
220 .reg_off = AO_CEC_CLK_CNTL_REG0,
225 .reg_off = AO_CEC_CLK_CNTL_REG1,
230 .reg_off = AO_CEC_CLK_CNTL_REG1,
235 .reg_off
[all...]
/linux/tools/testing/selftests/kvm/riscv/
H A Dget-reg-list.c246 /* reg_off is the offset into struct kvm_riscv_config */ in config_id_to_str()
247 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG); in config_id_to_str() local
251 switch (reg_off) { in config_id_to_str()
268 return strdup_printf("%lld /* UNKNOWN */", reg_off); in config_id_to_str()
273 /* reg_off is the offset into struct kvm_riscv_core */ in core_id_to_str()
274 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE); in core_id_to_str() local
278 switch (reg_off) { in core_id_to_str()
291 reg_off - KVM_REG_RISCV_CORE_REG(regs.t0)); in core_id_to_str()
294 reg_off - KVM_REG_RISCV_CORE_REG(regs.s0)); in core_id_to_str()
297 reg_off in core_id_to_str()
318 general_csr_id_to_str(__u64 reg_off) general_csr_id_to_str() argument
349 aia_csr_id_to_str(__u64 reg_off) aia_csr_id_to_str() argument
372 smstateen_csr_id_to_str(__u64 reg_off) smstateen_csr_id_to_str() argument
386 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); csr_id_to_str() local
408 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER); timer_id_to_str() local
429 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F); fp_f_id_to_str() local
447 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D); fp_d_id_to_str() local
465 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_VECTOR); vector_id_to_str() local
494 isa_ext_single_id_to_str(__u64 reg_off) isa_ext_single_id_to_str() argument
576 isa_ext_multi_id_to_str(__u64 reg_subtype,__u64 reg_off) isa_ext_multi_id_to_str() argument
595 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT); isa_ext_id_to_str() local
616 sbi_ext_single_id_to_str(__u64 reg_off) sbi_ext_single_id_to_str() argument
640 sbi_ext_multi_id_to_str(__u64 reg_subtype,__u64 reg_off) sbi_ext_multi_id_to_str() argument
659 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT); sbi_ext_id_to_str() local
677 sbi_sta_id_to_str(__u64 reg_off) sbi_sta_id_to_str() argument
688 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_STATE); sbi_id_to_str() local
[all...]
/linux/drivers/pinctrl/sunplus/
H A Dsppctl.c112 static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off) in sppctl_get_reg_and_bit_offset() argument
117 *reg_off = (offset / 32) * 4; in sppctl_get_reg_and_bit_offset()
123 static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off) in sppctl_get_moon_reg_and_bit_offset() argument
133 *reg_off = (offset / 16) * 4; in sppctl_get_moon_reg_and_bit_offset()
139 static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val) in sppctl_prep_moon_reg_and_offset() argument
143 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off); in sppctl_prep_moon_reg_and_offset()
227 static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz, in sppctl_gmx_set() argument
240 writel(reg, pctl->moon1_base + reg_off * 4); in sppctl_gmx_set()
264 u32 reg_off, bit_off, reg; in sppctl_first_get() local
266 bit_off = sppctl_get_reg_and_bit_offset(offset, &reg_off); in sppctl_first_get()
299 u32 reg_off, bit_off, reg; sppctl_master_get() local
310 u32 reg_off, bit_off, reg; sppctl_first_master_set() local
346 u32 reg_off, reg; sppctl_gpio_input_inv_set() local
355 u32 reg_off, reg; sppctl_gpio_output_inv_set() local
364 u32 reg_off, bit_off, reg; sppctl_gpio_output_od_get() local
376 u32 reg_off, reg; sppctl_gpio_output_od_set() local
385 u32 reg_off, bit_off, reg; sppctl_gpio_get_direction() local
396 u32 reg_off, bit_off, reg; sppctl_gpio_inv_get() local
417 u32 reg_off, reg; sppctl_gpio_direction_input() local
433 u32 reg_off, reg; sppctl_gpio_direction_output() local
456 u32 reg_off, bit_off, reg; sppctl_gpio_get() local
467 u32 reg_off, reg; sppctl_gpio_set() local
480 u32 reg_off, reg; sppctl_gpio_set_config() local
[all...]
/linux/drivers/pinctrl/
H A Dpinctrl-digicolor.c130 int bit_off, reg_off; in dc_set_mux() local
133 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
135 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
138 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
148 int bit_off, reg_off; in dc_pmx_request_gpio() local
151 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
153 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
171 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); in dc_gpio_direction_input() local
177 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
179 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
191 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); dc_gpio_direction_output() local
210 int reg_off = GP_INPUT(gpio/PINS_PER_COLLECTION); dc_gpio_get() local
222 int reg_off = GP_OUTPUT0(gpio/PINS_PER_COLLECTION); dc_gpio_set() local
[all...]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_1_7_msm8996.h26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
31 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
32 [DPU_CLK_CTRL_RGB2] = { .reg_off = 0x2bc, .bit_off = 4 },
33 [DPU_CLK_CTRL_RGB3] = { .reg_off = 0x2c4, .bit_off = 4 },
34 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA1] = { .reg_off
[all...]
H A Ddpu_3_0_msm8998.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
35 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
36 [DPU_CLK_CTRL_CURSOR1] = { .reg_off
[all...]
H A Ddpu_6_0_sm8250.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
34 [DPU_CLK_CTRL_WB2] = { .reg_off
[all...]
H A Ddpu_7_0_sm8350.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off
[all...]
H A Ddpu_8_1_sm8450.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off
[all...]
H A Ddpu_4_1_sdm670.h15 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
16 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
17 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
18 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
19 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
H A Ddpu_1_15_msm8917.h23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
24 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
25 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
27 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
H A Ddpu_6_4_sm6350.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
28 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
29 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
30 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_8_4_sa8775p.h24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
32 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off
[all...]
H A Ddpu_8_0_sc8280xp.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_5_1_sc8180x.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
35 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_5_3_sm6150.h24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
28 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
29 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_1_14_msm8937.h23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
24 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
25 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
27 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
/linux/sound/soc/tegra/
H A Dtegra210_mbdrc.c787 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; in tegra210_mbdrc_hw_params() local
790 reg_off + TEGRA210_MBDRC_CFG_RAM_CTRL, in tegra210_mbdrc_hw_params()
791 reg_off + TEGRA210_MBDRC_CFG_RAM_DATA, in tegra210_mbdrc_hw_params()
849 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; in tegra210_mbdrc_component_init() local
852 reg_off + TEGRA210_MBDRC_IIR_CFG, in tegra210_mbdrc_component_init()
858 reg_off + TEGRA210_MBDRC_IN_ATTACK, in tegra210_mbdrc_component_init()
864 reg_off + TEGRA210_MBDRC_IN_RELEASE, in tegra210_mbdrc_component_init()
870 reg_off + TEGRA210_MBDRC_FAST_ATTACK, in tegra210_mbdrc_component_init()
889 reg_off + TEGRA210_MBDRC_IN_THRESHOLD, in tegra210_mbdrc_component_init()
906 reg_off in tegra210_mbdrc_component_init()
[all...]
/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_main.h343 #define octep_write_csr(octep_dev, reg_off, value) \ argument
344 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off))
346 #define octep_write_csr64(octep_dev, reg_off, val64) \ argument
347 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off))
349 #define octep_read_csr(octep_dev, reg_off) \ argument
350 readl((octep_dev)->mmio[0].hw_addr + (reg_off))
352 #define octep_read_csr64(octep_dev, reg_off) \ argument
353 readq((octep_dev)->mmio[0].hw_addr + (reg_off))

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