| /linux/drivers/clk/nuvoton/ |
| H A D | clk-ma35d1-pll.c | 99 static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long parent_rate) in ma35d1_calc_pll_freq() argument
104 if (reg_ctl[1] & PLL_CTL1_BP) in ma35d1_calc_pll_freq()
107 n = FIELD_GET(PLL_CTL0_FBDIV, reg_ctl[0]); in ma35d1_calc_pll_freq()
108 m = FIELD_GET(PLL_CTL0_INDIV, reg_ctl[0]); in ma35d1_calc_pll_freq()
109 p = FIELD_GET(PLL_CTL1_OUTDIV, reg_ctl[1]); in ma35d1_calc_pll_freq()
115 x = FIELD_GET(PLL_CTL1_FRAC, reg_ctl[1]); in ma35d1_calc_pll_freq()
124 unsigned long parent_rate, u32 *reg_ctl, in ma35d1_pll_find_closest() argument
169 reg_ctl[0] = FIELD_PREP(PLL_CTL0_INDIV, m) | in ma35d1_pll_find_closest()
171 reg_ctl[1] = FIELD_PREP(PLL_CTL1_OUTDIV, p); in ma35d1_pll_find_closest()
189 u32 reg_ctl[3] = { 0 }; in ma35d1_clk_pll_set_rate() local
[all …]
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| /linux/drivers/clk/baikal-t1/ |
| H A D | ccu-div.c | 92 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_update_clkdiv()
102 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_update_clkdiv()
123 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_enable()
131 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_enable()
146 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_gate_enable()
159 regmap_update_bits(div->sys_regs, div->reg_ctl, CCU_DIV_CTL_EN, 0); in ccu_div_gate_disable()
168 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_gate_is_enabled()
179 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_buf_enable()
192 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_buf_disable()
202 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_buf_is_enabled()
[all …]
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| H A D | ccu-pll.c | 97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
100 return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val, in ccu_pll_reset()
117 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_enable()
122 regmap_write(pll->sys_regs, pll->reg_ctl, val | CCU_PLL_CTL_EN); in ccu_pll_enable()
138 regmap_update_bits(pll->sys_regs, pll->reg_ctl, CCU_PLL_CTL_EN, 0); in ccu_pll_disable()
147 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_is_enabled()
159 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_recalc_rate()
265 regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val); in ccu_pll_set_rate_reset()
299 regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val); in ccu_pll_set_rate_norst()
378 regmap_update_bits(pll->sys_regs, pll->reg_ctl + bit->reg, in ccu_pll_dbgfs_bit_set()
[all …]
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| H A D | ccu-pll.h | 56 unsigned int reg_ctl; member
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| H A D | ccu-div.h | 100 unsigned int reg_ctl; member
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| /linux/drivers/clocksource/ |
| H A D | timer-econet-en751221.c | 35 static inline void __iomem *reg_ctl(u32 timer_n) in reg_ctl() function
62 return ioread32(reg_ctl(cpu_id)) & ctl_bit_pending(cpu_id); in cevt_is_pending()
103 reg = ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu); in cevt_init_cpu()
104 iowrite32(reg, reg_ctl(cpu)); in cevt_init_cpu()
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| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_force_wake_types.h | 76 struct xe_reg reg_ctl; member
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dmc.c | 568 i915_reg_t reg_ctl, u32 *data_ctl, in fixup_dmc_evt() argument
571 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl)) in fixup_dmc_evt()
578 if (i915_mmio_reg_offset(reg_ctl) - i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) != in fixup_dmc_evt()
587 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { in fixup_dmc_evt()
601 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { in fixup_dmc_evt()
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