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Searched refs:qpc (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/net/ethernet/mellanox/mlx5/core/fpga/
H A Dconn.c497 static int mlx5_fpga_conn_create_wq(struct mlx5_fpga_conn *conn, void *qpc) in mlx5_fpga_conn_create_wq() argument
506 return mlx5_wq_qp_create(mdev, &wqp, qpc, &conn->qp.wq, in mlx5_fpga_conn_create_wq()
516 u32 temp_qpc[MLX5_ST_SZ_DW(qpc)] = {}; in mlx5_fpga_conn_create_qp()
517 void *in = NULL, *qpc; in mlx5_fpga_conn_create_qp() local
527 MLX5_SET(qpc, temp_qpc, log_rq_stride, ilog2(MLX5_SEND_WQE_DS) - 4); in mlx5_fpga_conn_create_qp()
528 MLX5_SET(qpc, temp_qpc, log_rq_size, ilog2(conn->qp.rq.size)); in mlx5_fpga_conn_create_qp()
529 MLX5_SET(qpc, temp_qpc, log_sq_size, ilog2(conn->qp.sq.size)); in mlx5_fpga_conn_create_qp()
555 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); in mlx5_fpga_conn_create_qp()
556 MLX5_SET(qpc, qpc, uar_page, fdev->conn_res.uar->index); in mlx5_fpga_conn_create_qp()
557 MLX5_SET(qpc, qpc, log_page_size, in mlx5_fpga_conn_create_qp()
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/linux/drivers/infiniband/hw/mlx5/
H A Dqp.c956 void *qpc; in _create_user_qp() local
1010 ubuffer->umem, qpc, log_page_size, in _create_user_qp()
1032 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); in _create_user_qp()
1036 MLX5_SET(qpc, qpc, log_page_size, in _create_user_qp()
1038 MLX5_SET(qpc, qpc, page_offset, page_offset_quantized); in _create_user_qp()
1040 MLX5_SET(qpc, qpc, uar_page, uar_index); in _create_user_qp()
1105 void *qpc; in _create_kernel_qp() local
1160 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); in _create_kernel_qp()
1161 MLX5_SET(qpc, qpc, uar_page, uar_index); in _create_kernel_qp()
1162 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); in _create_kernel_qp()
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H A Dqpc.c404 u32 opt_param_mask, void *qpc, in modify_qp_mbox_alloc() argument
424 memcpy(MLX5_ADDR_OF(typ##_in, in, qpc), _qpc, \ in modify_qp_mbox_alloc()
425 MLX5_ST_SZ_BYTES(qpc)); \ in modify_qp_mbox_alloc()
446 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
453 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
460 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
467 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
474 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
480 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
486 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
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H A DMakefile21 qpc.o \
H A Dqp.h29 void *qpc, struct mlx5_core_qp *qp, u32 *ece);
H A Ddevx.c752 void *qpc; in devx_set_umem_valid() local
754 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); in devx_set_umem_valid()
755 MLX5_SET(qpc, qpc, dbr_umem_valid, 1); in devx_set_umem_valid()
H A Dmlx5_ib.h48 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/
H A Ddr_send.c253 u32 temp_qpc[MLX5_ST_SZ_DW(qpc)] = {}; in dr_create_rc_qp()
257 void *qpc; in dr_create_rc_qp() local
276 MLX5_SET(qpc, temp_qpc, log_rq_stride, ilog2(MLX5_SEND_WQE_DS) - 4); in dr_create_rc_qp()
277 MLX5_SET(qpc, temp_qpc, log_rq_size, ilog2(dr_qp->rq.wqe_cnt)); in dr_create_rc_qp()
278 MLX5_SET(qpc, temp_qpc, log_sq_size, ilog2(dr_qp->sq.wqe_cnt)); in dr_create_rc_qp()
304 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); in dr_create_rc_qp()
305 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); in dr_create_rc_qp()
306 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); in dr_create_rc_qp()
307 MLX5_SET(qpc, qpc, isolate_vl_tc, attr->isolate_vl_tc); in dr_create_rc_qp()
308 MLX5_SET(qpc, qpc, pd, attr->pdn); in dr_create_rc_qp()
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/linux/drivers/vfio/pci/mlx5/
H A Dcmd.c1231 void *qpc; in mlx5vf_create_rc_qp() local
1266 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); in mlx5vf_create_rc_qp()
1267 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); in mlx5vf_create_rc_qp()
1268 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); in mlx5vf_create_rc_qp()
1269 MLX5_SET(qpc, qpc, pd, tracker->pdn); in mlx5vf_create_rc_qp()
1270 MLX5_SET(qpc, qpc, uar_page, tracker->uar->index); in mlx5vf_create_rc_qp()
1271 MLX5_SET(qpc, qpc, log_page_size, in mlx5vf_create_rc_qp()
1273 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(mdev)); in mlx5vf_create_rc_qp()
1275 MLX5_SET(qpc, qpc, user_index, 0xFFFFFF); in mlx5vf_create_rc_qp()
1276 MLX5_SET(qpc, qpc, no_sq, 1); in mlx5vf_create_rc_qp()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Ddebugfs.c311 u32 *qpc; in qp_read_field() local
326 qpc = MLX5_ADDR_OF(query_qp_out, out, qpc); in qp_read_field()
332 state = MLX5_GET(qpc, qpc, state); in qp_read_field()
337 param = (unsigned long)mlx5_qp_type_str(MLX5_GET(qpc, qpc, st)); in qp_read_field()
341 switch (MLX5_GET(qpc, qpc, mtu)) { in qp_read_field()
362 param = 1 << MLX5_GET(qpc, qpc, log_rq_size); in qp_read_field()
365 param = 1 << (MLX5_GET(qpc, qpc, log_rq_stride) + 4); in qp_read_field()
368 if (!MLX5_GET(qpc, qpc, no_sq)) in qp_read_field()
369 param = 1 << MLX5_GET(qpc, qpc, log_sq_size); in qp_read_field()
372 param = MLX5_GET(qpc, qpc, log_page_size) + 12; in qp_read_field()
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H A Dwq.c100 void *qpc, struct mlx5_wq_qp *wq, in mlx5_wq_qp_create() argument
103 u8 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride) + 4; in mlx5_wq_qp_create()
104 u8 log_rq_sz = MLX5_GET(qpc, qpc, log_rq_size); in mlx5_wq_qp_create()
106 u8 log_sq_sz = MLX5_GET(qpc, qpc, log_sq_size); in mlx5_wq_qp_create()
H A Dwq.h86 void *qpc, struct mlx5_wq_qp *wq,
/linux/drivers/net/ethernet/mellanox/mlx5/core/ipoib/
H A Dipoib.c229 u32 *qpc; in mlx5i_init_underlay_qp() local
231 qpc = MLX5_ADDR_OF(rst2init_qp_in, in, qpc); in mlx5i_init_underlay_qp()
233 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); in mlx5i_init_underlay_qp()
234 MLX5_SET(qpc, qpc, primary_address_path.pkey_index, in mlx5i_init_underlay_qp()
236 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); in mlx5i_init_underlay_qp()
237 MLX5_SET(qpc, qpc, q_key, IB_DEFAULT_Q_KEY); in mlx5i_init_underlay_qp()
298 void *qpc; in mlx5i_create_underlay_qp() local
305 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); in mlx5i_create_underlay_qp()
306 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(priv->mdev)); in mlx5i_create_underlay_qp()
307 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_UD); in mlx5i_create_underlay_qp()
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/linux/drivers/vdpa/mlx5/net/
H A Dmlx5_vnet.c378 void *qpc; in qp_prepare() local
382 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); in qp_prepare()
387 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); in qp_prepare()
388 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); in qp_prepare()
389 MLX5_SET(qpc, qpc, no_sq, 1); in qp_prepare()
393 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); in qp_prepare()
394 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); in qp_prepare()
395 MLX5_SET(qpc, qpc, pd, ndev->mvdev.res.pdn); in qp_prepare()
396 MLX5_SET(qpc, qpc, mtu, MLX5_QPC_MTU_256_BYTES); in qp_prepare()
397 MLX5_SET(qpc, qpc, uar_page, ndev->mvdev.res.uar->index); in qp_prepare()
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/linux/drivers/net/ethernet/mellanox/mlx4/
H A Dresource_tracker.c740 static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
747 struct mlx4_qp_context *qpc = inbox->buf + 8; in update_vport_qp_param() local
753 port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1; in update_vport_qp_param()
756 qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff; in update_vport_qp_param()
758 err = handle_counter(dev, qpc, slave, port); in update_vport_qp_param()
776 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN); in update_vport_qp_param()
787 qpc->pri_path.vlan_control &= in update_vport_qp_param()
791 qpc->pri_path.vlan_control |= in update_vport_qp_param()
804 qpc->pri_path.vlan_control |= in update_vport_qp_param()
810 qpc->pri_path.vlan_control |= in update_vport_qp_param()
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/linux/drivers/infiniband/hw/hns/
H A Dhns_roce_restrack.c100 struct hns_roce_v2_qp_context qpc; in hns_roce_fill_res_qp_entry_raw() member
109 ret = hr_dev->hw->query_qpc(hr_dev, hr_qp->qpn, &context.qpc); in hns_roce_fill_res_qp_entry_raw()
/linux/include/linux/mlx5/
H A Dmlx5_ifc.h5058 struct mlx5_ifc_qpc_bits qpc; member
5088 struct mlx5_ifc_qpc_bits qpc; member
5318 struct mlx5_ifc_qpc_bits qpc; member
5349 struct mlx5_ifc_qpc_bits qpc; member
5380 struct mlx5_ifc_qpc_bits qpc; member
5976 struct mlx5_ifc_qpc_bits qpc; member
8315 struct mlx5_ifc_qpc_bits qpc; member
8346 struct mlx5_ifc_qpc_bits qpc; member
9435 struct mlx5_ifc_qpc_bits qpc; member
H A Ddevice.h301 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)