| /linux/drivers/pps/ |
| H A D | pps.c | 40 struct pps_device *pps = file->private_data; in pps_cdev_poll() local
42 poll_wait(file, &pps->queue, wait); in pps_cdev_poll()
44 if (pps->last_fetched_ev == pps->last_ev) in pps_cdev_poll()
52 struct pps_device *pps = file->private_data; in pps_cdev_fasync() local
53 return fasync_helper(fd, file, on, &pps->async_queue); in pps_cdev_fasync()
56 static int pps_cdev_pps_fetch(struct pps_device *pps, struct pps_fdata *fdata) in pps_cdev_pps_fetch() argument
58 unsigned int ev = pps->last_ev; in pps_cdev_pps_fetch()
63 err = wait_event_interruptible(pps->queue, in pps_cdev_pps_fetch()
64 ev != pps->last_ev); in pps_cdev_pps_fetch()
68 dev_dbg(&pps->dev, "timeout %lld.%09d\n", in pps_cdev_pps_fetch()
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| H A D | kapi.c | 41 static void pps_echo_client_default(struct pps_device *pps, int event, in pps_echo_client_default() argument
44 dev_info(&pps->dev, "echo %s %s\n", in pps_echo_client_default()
68 struct pps_device *pps; in pps_register_source() local
86 pps = kzalloc_obj(struct pps_device); in pps_register_source()
87 if (pps == NULL) { in pps_register_source()
95 pps->params.api_version = PPS_API_VERS; in pps_register_source()
96 pps->params.mode = default_params; in pps_register_source()
97 pps->info = *info; in pps_register_source()
100 if ((pps->info.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR)) && in pps_register_source()
101 pps->info.echo == NULL) in pps_register_source()
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| H A D | sysfs.c | 21 struct pps_device *pps = dev_get_drvdata(dev); in assert_show() local
23 if (!(pps->info.mode & PPS_CAPTUREASSERT)) in assert_show()
27 (long long) pps->assert_tu.sec, pps->assert_tu.nsec, in assert_show()
28 pps->assert_sequence); in assert_show()
35 struct pps_device *pps = dev_get_drvdata(dev); in clear_show() local
37 if (!(pps->info.mode & PPS_CAPTURECLEAR)) in clear_show()
41 (long long) pps->clear_tu.sec, pps->clear_tu.nsec, in clear_show()
42 pps->clear_sequence); in clear_show()
49 struct pps_device *pps = dev_get_drvdata(dev); in mode_show() local
51 return sprintf(buf, "%4x\n", pps->info.mode); in mode_show()
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| H A D | kc.c | 36 int pps_kc_bind(struct pps_device *pps, struct pps_bind_args *bind_args) in pps_kc_bind() argument
42 if (pps_kc_hardpps_dev == pps) { in pps_kc_bind()
46 dev_info(&pps->dev, "unbound kernel" in pps_kc_bind()
50 dev_err(&pps->dev, "selected kernel consumer" in pps_kc_bind()
56 pps_kc_hardpps_dev == pps) { in pps_kc_bind()
58 pps_kc_hardpps_dev = pps; in pps_kc_bind()
60 dev_info(&pps->dev, "bound kernel consumer: " in pps_kc_bind()
64 dev_err(&pps->dev, "another kernel consumer" in pps_kc_bind()
79 void pps_kc_remove(struct pps_device *pps) in pps_kc_remove() argument
82 if (pps == pps_kc_hardpps_dev) { in pps_kc_remove()
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| H A D | kc.h | 16 extern int pps_kc_bind(struct pps_device *pps,
18 extern void pps_kc_remove(struct pps_device *pps);
19 extern void pps_kc_event(struct pps_device *pps,
25 static inline int pps_kc_bind(struct pps_device *pps, in pps_kc_bind() argument
27 static inline void pps_kc_remove(struct pps_device *pps) {} in pps_kc_remove() argument
28 static inline void pps_kc_event(struct pps_device *pps, in pps_kc_event() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| H A D | dcn20_dsc.c | 201 dsc_log_pps(dsc, &dsc20->reg_vals.pps); in dsc2_set_config()
220 …drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps… in dsc2_get_packed_pps()
221 dsc_log_pps(dsc, &dsc_reg_vals.pps); in dsc2_get_packed_pps()
289 void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps) in dsc_log_pps() argument
292 int bits_per_pixel = pps->bits_per_pixel; in dsc_log_pps()
294 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major); in dsc_log_pps()
295 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor); in dsc_log_pps()
296 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component); in dsc_log_pps()
297 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); in dsc_log_pps()
298 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); in dsc_log_pps()
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| H A D | dcn401_dsc.c | 135 dsc_log_pps(dsc, &dsc401->reg_vals.pps); in dsc401_set_config()
214 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); in dsc_write_to_registers()
247 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, in dsc_write_to_registers()
248 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, in dsc_write_to_registers()
249 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); in dsc_write_to_registers()
260 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, in dsc_write_to_registers()
263 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); in dsc_write_to_registers()
266 PIC_WIDTH, reg_vals->pps.pic_width, in dsc_write_to_registers()
267 PIC_HEIGHT, reg_vals->pps.pic_height); in dsc_write_to_registers()
270 SLICE_WIDTH, reg_vals->pps.slice_width, in dsc_write_to_registers()
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| /linux/drivers/media/platform/rockchip/rkvdec/ |
| H A D | rkvdec-vdpu383-h264.c | 116 struct rkvdec_pps pps; member
133 static noinline_for_stack void set_field_order_cnt(struct rkvdec_pps *pps, const struct v4l2_h264_d… in set_field_order_cnt() argument
135 pps->top_field_order_cnt0 = dpb[0].top_field_order_cnt; in set_field_order_cnt()
136 pps->bot_field_order_cnt0 = dpb[0].bottom_field_order_cnt; in set_field_order_cnt()
137 pps->top_field_order_cnt1 = dpb[1].top_field_order_cnt; in set_field_order_cnt()
138 pps->bot_field_order_cnt1 = dpb[1].bottom_field_order_cnt; in set_field_order_cnt()
139 pps->top_field_order_cnt2 = dpb[2].top_field_order_cnt; in set_field_order_cnt()
140 pps->bot_field_order_cnt2 = dpb[2].bottom_field_order_cnt; in set_field_order_cnt()
141 pps->top_field_order_cnt3 = dpb[3].top_field_order_cnt; in set_field_order_cnt()
142 pps->bot_field_order_cnt3 = dpb[3].bottom_field_order_cnt; in set_field_order_cnt()
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| H A D | rkvdec-vdpu381-hevc.c | 101 struct rkvdec_hevc_pps pps; member
129 const struct v4l2_ctrl_hevc_pps *pps = run->pps; in assemble_hw_pps() local
148 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; in assemble_hw_pps()
202 hw_ps->pps.picture_parameters_set_id = pps->pic_parameter_set_id; in assemble_hw_pps()
203 hw_ps->pps.seq_parameters_set_id_pps = sps->seq_parameter_set_id; in assemble_hw_pps()
204 hw_ps->pps.dependent_slice_segments_enabled_flag = in assemble_hw_pps()
205 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED); in assemble_hw_pps()
206 hw_ps->pps.output_flag_present_flag = in assemble_hw_pps()
207 !!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT); in assemble_hw_pps()
208 hw_ps->pps.num_extra_slice_header_bits = pps->num_extra_slice_header_bits; in assemble_hw_pps()
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| H A D | rkvdec-vdpu381-h264.c | 69 struct rkvdec_pps pps; member
91 const struct v4l2_ctrl_h264_pps *pps = run->pps; in assemble_hw_pps() local
106 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; in assemble_hw_pps()
145 hw_ps->pps.pic_parameter_set_id = pps->pic_parameter_set_id; in assemble_hw_pps()
146 hw_ps->pps.pps_seq_parameter_set_id = pps->seq_parameter_set_id; in assemble_hw_pps()
147 hw_ps->pps.entropy_coding_mode_flag = in assemble_hw_pps()
148 !!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); in assemble_hw_pps()
149 hw_ps->pps.bottom_field_pic_order_in_frame_present_flag = in assemble_hw_pps()
150 !!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); in assemble_hw_pps()
151 hw_ps->pps.num_ref_idx_l0_default_active_minus1 = in assemble_hw_pps()
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| H A D | rkvdec-hevc.c | 145 const struct v4l2_ctrl_hevc_pps *pps = run->pps; in assemble_hw_pps() local
159 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; in assemble_hw_pps()
214 WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); in assemble_hw_pps()
216 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), in assemble_hw_pps()
218 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), in assemble_hw_pps()
220 WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS); in assemble_hw_pps()
221 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED), in assemble_hw_pps()
223 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT), in assemble_hw_pps()
225 WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1, in assemble_hw_pps()
227 WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1, in assemble_hw_pps()
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| H A D | rkvdec-vdpu383-hevc.c | 224 const struct v4l2_ctrl_hevc_pps *pps = run->pps; in assemble_hw_pps() local
296 hw_ps->picture_parameters_set_id = pps->pic_parameter_set_id; in assemble_hw_pps()
299 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED); in assemble_hw_pps()
300 hw_ps->output_flag_present_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT); in assemble_hw_pps()
301 hw_ps->num_extra_slice_header_bits = pps->num_extra_slice_header_bits; in assemble_hw_pps()
303 !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED); in assemble_hw_pps()
304 hw_ps->cabac_init_present_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT); in assemble_hw_pps()
305 hw_ps->num_ref_idx_l0_default_active = pps->num_ref_idx_l0_default_active_minus1 + 1; in assemble_hw_pps()
306 hw_ps->num_ref_idx_l1_default_active = pps->num_ref_idx_l1_default_active_minus1 + 1; in assemble_hw_pps()
307 hw_ps->init_qp_minus26 = pps->init_qp_minus26; in assemble_hw_pps()
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/ |
| H A D | rc_calc.c | 40 void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) in calc_rc_params() argument
46 u16 drm_bpp = pps->bits_per_pixel; in calc_rc_params()
47 int slice_width = pps->slice_width; in calc_rc_params()
48 int slice_height = pps->slice_height; in calc_rc_params()
50 mode = pps->convert_rgb ? CM_RGB : (pps->simple_422 ? CM_444 : in calc_rc_params()
51 (pps->native_422 ? CM_422 : in calc_rc_params()
52 pps->native_420 ? CM_420 : CM_444)); in calc_rc_params()
53 bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10) in calc_rc_params()
56 is_navite_422_or_420 = pps->native_422 || pps->native_420; in calc_rc_params()
61 pps->dsc_version_minor); in calc_rc_params()
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| /linux/drivers/pps/clients/ |
| H A D | pps-ldisc.c | 18 struct pps_device *pps; in pps_tty_dcd_change() local
23 pps = pps_lookup_dev(tty); in pps_tty_dcd_change()
28 if (WARN_ON_ONCE(pps == NULL)) in pps_tty_dcd_change()
32 pps_event(pps, &ts, active ? PPS_CAPTUREASSERT : in pps_tty_dcd_change()
35 dev_dbg(&pps->dev, "PPS %s at %lu\n", in pps_tty_dcd_change()
46 struct pps_device *pps; in pps_tty_open() local
57 pps = pps_register_source(&info, PPS_CAPTUREBOTH | \ in pps_tty_open()
59 if (IS_ERR(pps)) { in pps_tty_open()
61 return PTR_ERR(pps); in pps_tty_open()
63 pps->lookup_cookie = tty; in pps_tty_open()
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| H A D | pps-ktimer.c | 21 static struct pps_device *pps; variable
35 pps_event(pps, &ts, PPS_CAPTUREASSERT, NULL); in pps_ktimer_event()
59 dev_dbg(&pps->dev, "ktimer PPS source unregistered\n"); in pps_ktimer_exit()
62 pps_unregister_source(pps); in pps_ktimer_exit()
67 pps = pps_register_source(&pps_ktimer_info, in pps_ktimer_init()
69 if (IS_ERR(pps)) { in pps_ktimer_init()
71 return PTR_ERR(pps); in pps_ktimer_init()
77 dev_dbg(&pps->dev, "ktimer PPS source registered\n"); in pps_ktimer_init()
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| H A D | pps-gpio.c | 29 struct pps_device *pps; /* PPS source device */ member
60 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
64 pps_event(info->pps, &ts, PPS_CAPTURECLEAR, data); in pps_gpio_irq_handler()
66 dev_warn_ratelimited(&info->pps->dev, "IRQ did not trigger any PPS event\n"); in pps_gpio_irq_handler()
72 static void pps_gpio_echo(struct pps_device *pps, int event, void *data) in pps_gpio_echo() argument
79 if (pps->params.mode & PPS_ECHOASSERT) in pps_gpio_echo()
84 if (pps->params.mode & PPS_ECHOCLEAR) in pps_gpio_echo()
90 if (info->pps->params.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR)) { in pps_gpio_echo()
205 data->pps = pps_register_source(&data->info, pps_default_params); in pps_gpio_probe()
206 if (IS_ERR(data->pps)) { in pps_gpio_probe()
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| /linux/drivers/media/platform/allegro-dvt/ |
| H A D | nal-hevc.c | 430 static void nal_hevc_rbsp_pps(struct rbsp *rbsp, struct nal_hevc_pps *pps) in nal_hevc_rbsp_pps() argument
434 rbsp_uev(rbsp, &pps->pps_pic_parameter_set_id); in nal_hevc_rbsp_pps()
435 rbsp_uev(rbsp, &pps->pps_seq_parameter_set_id); in nal_hevc_rbsp_pps()
436 rbsp_bit(rbsp, &pps->dependent_slice_segments_enabled_flag); in nal_hevc_rbsp_pps()
437 rbsp_bit(rbsp, &pps->output_flag_present_flag); in nal_hevc_rbsp_pps()
438 rbsp_bits(rbsp, 3, &pps->num_extra_slice_header_bits); in nal_hevc_rbsp_pps()
439 rbsp_bit(rbsp, &pps->sign_data_hiding_enabled_flag); in nal_hevc_rbsp_pps()
440 rbsp_bit(rbsp, &pps->cabac_init_present_flag); in nal_hevc_rbsp_pps()
441 rbsp_uev(rbsp, &pps->num_ref_idx_l0_default_active_minus1); in nal_hevc_rbsp_pps()
442 rbsp_uev(rbsp, &pps->num_ref_idx_l1_default_active_minus1); in nal_hevc_rbsp_pps()
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| H A D | nal-h264.c | 283 static void nal_h264_rbsp_pps(struct rbsp *rbsp, struct nal_h264_pps *pps) in nal_h264_rbsp_pps() argument
287 rbsp_uev(rbsp, &pps->pic_parameter_set_id); in nal_h264_rbsp_pps()
288 rbsp_uev(rbsp, &pps->seq_parameter_set_id); in nal_h264_rbsp_pps()
289 rbsp_bit(rbsp, &pps->entropy_coding_mode_flag); in nal_h264_rbsp_pps()
290 rbsp_bit(rbsp, &pps->bottom_field_pic_order_in_frame_present_flag); in nal_h264_rbsp_pps()
291 rbsp_uev(rbsp, &pps->num_slice_groups_minus1); in nal_h264_rbsp_pps()
292 if (pps->num_slice_groups_minus1 > 0) { in nal_h264_rbsp_pps()
293 rbsp_uev(rbsp, &pps->slice_group_map_type); in nal_h264_rbsp_pps()
294 switch (pps->slice_group_map_type) { in nal_h264_rbsp_pps()
296 for (i = 0; i < pps->num_slice_groups_minus1; i++) in nal_h264_rbsp_pps()
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| /linux/drivers/media/platform/verisilicon/ |
| H A D | hantro_g2_hevc_dec.c | 15 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps; in prepare_tile_info_buffer() local
18 unsigned int num_tile_rows = pps->num_tile_rows_minus1 + 1; in prepare_tile_info_buffer()
19 unsigned int num_tile_cols = pps->num_tile_columns_minus1 + 1; in prepare_tile_info_buffer()
25 tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED); in prepare_tile_info_buffer()
26 uniform_spacing = !!(pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING); in prepare_tile_info_buffer()
57 h = pps->row_height_minus1[i] + 1; in prepare_tile_info_buffer()
62 tmp_w += pps->column_width_minus1[j] + 1; in prepare_tile_info_buffer()
63 *p++ = pps->column_width_minus1[j] + 1; in prepare_tile_info_buffer()
86 (pps->column_width_minus1[0] + 1) == 1 && in prepare_tile_info_buffer()
111 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps; in compute_header_skip_length() local
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| H A D | hantro_g1_h264_dec.c | 27 const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; in set_params() local
58 reg = G1_REG_DEC_CTRL2_CH_QP_OFFSET(pps->chroma_qp_index_offset) | in set_params()
59 G1_REG_DEC_CTRL2_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset); in set_params()
61 if (pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT) in set_params()
69 G1_REG_DEC_CTRL3_INIT_QP(pps->pic_init_qp_minus26 + 26) | in set_params()
76 G1_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc); in set_params()
77 if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) in set_params()
83 if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) in set_params()
90 if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) in set_params()
92 if (pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) in set_params()
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-pps | 1 What: /sys/class/pps/
5 The /sys/class/pps/ directory will contain files and
9 What: /sys/class/pps/ppsX/
13 The /sys/class/pps/ppsX/ directory is related to X-th
17 What: /sys/class/pps/ppsX/assert
21 The /sys/class/pps/ppsX/assert file reports the assert events
29 What: /sys/class/pps/ppsX/clear
33 The /sys/class/pps/ppsX/clear file reports the clear events
41 What: /sys/class/pps/ppsX/mode
45 The /sys/class/pps/ppsX/mode file reports the functioning
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| H A D | sysfs-pps-gen | 1 What: /sys/class/pps-gen/
6 The /sys/class/pps-gen/ directory contains files and
10 What: /sys/class/pps-gen/pps-genX/
15 The /sys/class/pps-gen/pps-genX/ directory is related to X-th
19 What: /sys/class/pps-gen/pps-genX/enable
27 What: /sys/class/pps-gen/pps-genX/system
36 What: /sys/class/pps-gen/pps-genX/time
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| /linux/samples/bpf/ |
| H A D | xdp_sample_user.c | 60 #define PPS(pps) pps, "pkt/s" argument
123 __u64 pps; member
137 __u64 pps; member
592 __u64 pps = 0; in calc_pps() local
596 pps = sample_round(packets / period_); in calc_pps()
598 return pps; in calc_pps()
604 __u64 pps = 0; in calc_drop_pps() local
608 pps = sample_round(packets / period_); in calc_drop_pps()
610 return pps; in calc_drop_pps()
616 __u64 pps = 0; in calc_errs_pps() local
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| /linux/drivers/staging/media/sunxi/cedrus/ |
| H A D | cedrus_h265.c | 364 const struct v4l2_ctrl_hevc_pps *pps; in cedrus_h265_write_tiles() local
370 pps = run->h265.pps; in cedrus_h265_write_tiles()
375 for (x = 0, tx = 0; tx < pps->num_tile_columns_minus1 + 1; tx++) { in cedrus_h265_write_tiles()
376 if (x + pps->column_width_minus1[tx] + 1 > ctb_addr_x) in cedrus_h265_write_tiles()
379 x += pps->column_width_minus1[tx] + 1; in cedrus_h265_write_tiles()
382 for (y = 0, ty = 0; ty < pps->num_tile_rows_minus1 + 1; ty++) { in cedrus_h265_write_tiles()
383 if (y + pps->row_height_minus1[ty] + 1 > ctb_addr_y) in cedrus_h265_write_tiles()
386 y += pps->row_height_minus1[ty] + 1; in cedrus_h265_write_tiles()
391 ((y + pps->row_height_minus1[ty]) << 16) | in cedrus_h265_write_tiles()
392 ((x + pps->column_width_minus1[tx]) << 0)); in cedrus_h265_write_tiles()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_lvds.c | 158 struct intel_lvds_pps *pps) in intel_lvds_pps_get_hw_state() argument
162 pps->powerdown_on_reset = intel_de_read(display, in intel_lvds_pps_get_hw_state()
166 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
167 pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
168 pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
171 pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
172 pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
175 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
185 pps->delays.power_cycle = val * 1000; in intel_lvds_pps_get_hw_state()
188 pps->delays.power_up == 0 && in intel_lvds_pps_get_hw_state()
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