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Searched refs:min_sclk (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu10_hwmgr.c627 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; in smu10_dpm_force_dpm_level() local
638 if (min_sclk < data->gfx_min_freq_limit) in smu10_dpm_force_dpm_level()
639 min_sclk = data->gfx_min_freq_limit; in smu10_dpm_force_dpm_level()
641 min_sclk /= 100; /* transfer 10KHz to MHz */ in smu10_dpm_force_dpm_level()
701 min_sclk, in smu10_dpm_force_dpm_level()
705 min_sclk, in smu10_dpm_force_dpm_level()
780 min_sclk, in smu10_dpm_force_dpm_level()
H A Dvega12_hwmgr.c804 hwmgr->default_compute_power_profile.min_sclk =
2685 uint32_t min_sclk, uint32_t min_mclk)
2693 dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
/linux/drivers/gpu/drm/radeon/
H A Dtrinity_dpm.h78 u32 min_sclk; member
H A Dtrinity_dpm.c1355 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ in trinity_patch_thermal_state()
1494 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */ in trinity_apply_state_adjust_rules() local
1495 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ in trinity_apply_state_adjust_rules()
1518 if (ps->levels[i].sclk < min_sclk) in trinity_apply_state_adjust_rules()
1520 trinity_get_valid_engine_clock(rdev, min_sclk); in trinity_apply_state_adjust_rules()
1819 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_7.ulMinEngineClock); in trinity_parse_sys_info_table()
H A Dsumo_dpm.h83 u32 min_sclk; member
H A Dsumo_dpm.c1045 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ in sumo_patch_thermal_state()
1092 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */ in sumo_apply_state_adjust_rules() local
1093 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ in sumo_apply_state_adjust_rules()
1113 if (ps->levels[i].sclk < min_sclk) in sumo_apply_state_adjust_rules()
1115 sumo_get_valid_engine_clock(rdev, min_sclk); in sumo_apply_state_adjust_rules()
1676 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock); in sumo_parse_sys_info_table()
H A Dni_dpm.c2464 u32 min_sclk; in ni_populate_power_containment_values() local
2515 min_sclk = max_sclk; in ni_populate_power_containment_values()
2517 min_sclk = prev_sclk; in ni_populate_power_containment_values()
2519 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; in ni_populate_power_containment_values()
2521 if (min_sclk < state->performance_levels[0].sclk) in ni_populate_power_containment_values()
2522 min_sclk = state->performance_levels[0].sclk; in ni_populate_power_containment_values()
2524 if (min_sclk == 0) in ni_populate_power_containment_values()
2528 (u8)((NISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); in ni_populate_power_containment_values()
H A Dsi_dpm.c2232 u32 min_sclk; in si_populate_power_containment_values() local
2272 min_sclk = max_sclk; in si_populate_power_containment_values()
2274 min_sclk = prev_sclk; in si_populate_power_containment_values()
2276 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; in si_populate_power_containment_values()
2279 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2280 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2282 if (min_sclk == 0) in si_populate_power_containment_values()
2306 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma… in si_populate_power_containment_values()
H A Dkv_dpm.c1940 u32 min_sclk = 10000; /* ??? */ in kv_apply_state_adjust_rules() local
1959 sclk = min_sclk; in kv_apply_state_adjust_rules()
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c2402 u32 min_sclk; in si_populate_power_containment_values() local
2442 min_sclk = max_sclk; in si_populate_power_containment_values()
2444 min_sclk = prev_sclk; in si_populate_power_containment_values()
2446 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; in si_populate_power_containment_values()
2448 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2449 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2451 if (min_sclk == 0) in si_populate_power_containment_values()
2475 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma… in si_populate_power_containment_values()
H A Dkv_dpm.c2202 u32 min_sclk = 10000; /* ??? */ in kv_apply_state_adjust_rules() local
2221 sclk = min_sclk; in kv_apply_state_adjust_rules()