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Searched refs:gmu (Results 1 – 25 of 33) sorted by relevance

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/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gmu.c21 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) in a6xx_gmu_fault() argument
23 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fault()
28 gmu->hung = true; in a6xx_gmu_fault()
39 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq() local
42 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); in a6xx_gmu_irq()
43 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); in a6xx_gmu_irq()
46 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); in a6xx_gmu_irq()
48 a6xx_gmu_fault(gmu); in a6xx_gmu_irq()
52 dev_err_ratelimited(gmu in a6xx_gmu_irq()
63 struct a6xx_gmu *gmu = data; a6xx_hfi_irq() local
78 a6xx_gmu_sptprac_is_on(struct a6xx_gmu * gmu) a6xx_gmu_sptprac_is_on() argument
94 a6xx_gmu_gx_is_on(struct a6xx_gmu * gmu) a6xx_gmu_gx_is_on() argument
115 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_set_freq() local
209 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_get_freq() local
214 a6xx_gmu_check_idle_level(struct a6xx_gmu * gmu) a6xx_gmu_check_idle_level() argument
235 a6xx_gmu_wait_for_idle(struct a6xx_gmu * gmu) a6xx_gmu_wait_for_idle() argument
240 a6xx_gmu_start(struct a6xx_gmu * gmu) a6xx_gmu_start() argument
278 a6xx_gmu_hfi_start(struct a6xx_gmu * gmu) a6xx_gmu_hfi_start() argument
338 a6xx_gmu_set_oob(struct a6xx_gmu * gmu,enum a6xx_gmu_oob_state state) a6xx_gmu_set_oob() argument
383 a6xx_gmu_clear_oob(struct a6xx_gmu * gmu,enum a6xx_gmu_oob_state state) a6xx_gmu_clear_oob() argument
401 a6xx_sptprac_enable(struct a6xx_gmu * gmu) a6xx_sptprac_enable() argument
423 a6xx_sptprac_disable(struct a6xx_gmu * gmu) a6xx_sptprac_disable() argument
445 a6xx_gmu_gfx_rail_on(struct a6xx_gmu * gmu) a6xx_gmu_gfx_rail_on() argument
462 a6xx_gemnoc_workaround(struct a6xx_gmu * gmu) a6xx_gemnoc_workaround() argument
477 a6xx_gmu_notify_slumber(struct a6xx_gmu * gmu) a6xx_gmu_notify_slumber() argument
516 a6xx_rpmh_start(struct a6xx_gmu * gmu) a6xx_rpmh_start() argument
543 a6xx_rpmh_stop(struct a6xx_gmu * gmu) a6xx_rpmh_stop() argument
566 a6xx_gmu_rpmh_init(struct a6xx_gmu * gmu) a6xx_gmu_rpmh_init() argument
702 a6xx_gmu_power_config(struct a6xx_gmu * gmu) a6xx_gmu_power_config() argument
761 a6xx_gmu_fw_load(struct a6xx_gmu * gmu) a6xx_gmu_fw_load() argument
824 a6xx_gmu_fw_start(struct a6xx_gmu * gmu,unsigned int state) a6xx_gmu_fw_start() argument
955 a6xx_gmu_irq_disable(struct a6xx_gmu * gmu) a6xx_gmu_irq_disable() argument
964 a6xx_gmu_rpmh_off(struct a6xx_gmu * gmu) a6xx_gmu_rpmh_off() argument
986 a6xx_gmu_force_off(struct a6xx_gmu * gmu) a6xx_gmu_force_off() argument
1028 a6xx_gmu_set_initial_freq(struct msm_gpu * gpu,struct a6xx_gmu * gmu) a6xx_gmu_set_initial_freq() argument
1042 a6xx_gmu_set_initial_bw(struct msm_gpu * gpu,struct a6xx_gmu * gmu) a6xx_gmu_set_initial_bw() argument
1059 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_resume() local
1143 a6xx_gmu_isidle(struct a6xx_gmu * gmu) a6xx_gmu_isidle() argument
1159 a6xx_gmu_shutdown(struct a6xx_gmu * gmu) a6xx_gmu_shutdown() argument
1227 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_stop() local
1260 a6xx_gmu_memory_free(struct a6xx_gmu * gmu) a6xx_gmu_memory_free() argument
1275 a6xx_gmu_memory_alloc(struct a6xx_gmu * gmu,struct a6xx_gmu_bo * bo,size_t size,u64 iova,const char * name) a6xx_gmu_memory_alloc() argument
1316 a6xx_gmu_memory_probe(struct drm_device * drm,struct a6xx_gmu * gmu) a6xx_gmu_memory_probe() argument
1349 a6xx_gmu_rpmh_bw_votes_init(struct adreno_gpu * adreno_gpu,const struct a6xx_info * info,struct a6xx_gmu * gmu) a6xx_gmu_rpmh_bw_votes_init() argument
1538 a6xx_gmu_rpmh_votes_init(struct a6xx_gmu * gmu) a6xx_gmu_rpmh_votes_init() argument
1625 a6xx_gmu_pwrlevels_probe(struct a6xx_gmu * gmu) a6xx_gmu_pwrlevels_probe() argument
1668 a6xx_gmu_acd_probe(struct a6xx_gmu * gmu) a6xx_gmu_acd_probe() argument
1737 a6xx_gmu_clocks_probe(struct a6xx_gmu * gmu) a6xx_gmu_clocks_probe() argument
1776 a6xx_gmu_get_irq(struct a6xx_gmu * gmu,struct platform_device * pdev,const char * name,irq_handler_t handler) a6xx_gmu_get_irq() argument
1796 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_remove() local
1845 struct a6xx_gmu *gmu = container_of(nb, struct a6xx_gmu, pd_nb); cxpd_notifier_cb() local
1856 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_wrapper_init() local
1921 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_init() local
[all...]
H A Da6xx_hfi.c29 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu, in a6xx_hfi_queue_read() argument
60 if (!gmu->legacy) in a6xx_hfi_queue_read()
67 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, in a6xx_hfi_queue_write() argument
91 if (!gmu->legacy) { in a6xx_hfi_queue_write()
99 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
103 static int a6xx_hfi_wait_for_msg_interrupt(struct a6xx_gmu *gmu, u32 id, u32 seqnum) in a6xx_hfi_wait_for_msg_interrupt() argument
109 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_hfi_wait_for_msg_interrupt()
113 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_msg_interrupt()
120 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, in a6xx_hfi_wait_for_msg_interrupt()
126 static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u3 argument
189 a6xx_hfi_send_msg(struct a6xx_gmu * gmu,int id,void * data,u32 size,u32 * payload,u32 payload_size) a6xx_hfi_send_msg() argument
212 a6xx_hfi_send_gmu_init(struct a6xx_gmu * gmu,int boot_state) a6xx_hfi_send_gmu_init() argument
224 a6xx_hfi_get_fw_version(struct a6xx_gmu * gmu,u32 * version) a6xx_hfi_get_fw_version() argument
235 a6xx_hfi_send_perf_table_v1(struct a6xx_gmu * gmu) a6xx_hfi_send_perf_table_v1() argument
257 a6xx_hfi_send_perf_table(struct a6xx_gmu * gmu) a6xx_hfi_send_perf_table() argument
280 a6xx_generate_bw_table(const struct a6xx_info * info,struct a6xx_gmu * gmu,struct a6xx_hfi_msg_bw_table * msg) a6xx_generate_bw_table() argument
722 a6xx_hfi_send_bw_table(struct a6xx_gmu * gmu) a6xx_hfi_send_bw_table() argument
770 a6xx_hfi_enable_acd(struct a6xx_gmu * gmu) a6xx_hfi_enable_acd() argument
800 a6xx_hfi_send_test(struct a6xx_gmu * gmu) a6xx_hfi_send_test() argument
808 a6xx_hfi_send_start(struct a6xx_gmu * gmu) a6xx_hfi_send_start() argument
816 a6xx_hfi_send_core_fw_start(struct a6xx_gmu * gmu) a6xx_hfi_send_core_fw_start() argument
824 a6xx_hfi_set_freq(struct a6xx_gmu * gmu,u32 freq_index,u32 bw_index) a6xx_hfi_set_freq() argument
836 a6xx_hfi_send_prep_slumber(struct a6xx_gmu * gmu) a6xx_hfi_send_prep_slumber() argument
846 a6xx_hfi_start_v1(struct a6xx_gmu * gmu,int boot_state) a6xx_hfi_start_v1() argument
881 a6xx_hfi_start(struct a6xx_gmu * gmu,int boot_state) a6xx_hfi_start() argument
916 a6xx_hfi_stop(struct a6xx_gmu * gmu) a6xx_hfi_stop() argument
964 a6xx_hfi_init(struct a6xx_gmu * gmu) a6xx_hfi_init() argument
[all...]
H A Da6xx_gmu.h122 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) in gmu_read() argument
124 return readl(gmu->mmio + (offset << 2)); in gmu_read()
127 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) in gmu_write() argument
129 writel(value, gmu->mmio + (offset << 2)); in gmu_write()
133 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size) in gmu_write_bulk() argument
135 memcpy_toio(gmu->mmio + (offset << 2), data, size); in gmu_write_bulk()
139 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) in gmu_rmw() argument
141 u32 val = gmu_read(gmu, reg); in gmu_rmw()
145 gmu_write(gmu, reg, val | or); in gmu_rmw()
148 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u3 argument
158 gmu_poll_timeout(gmu,addr,val,cond,interval,timeout) global() argument
162 gmu_read_rscc(struct a6xx_gmu * gmu,u32 offset) gmu_read_rscc() argument
167 gmu_write_rscc(struct a6xx_gmu * gmu,u32 offset,u32 value) gmu_write_rscc() argument
172 gmu_poll_timeout_rscc(gmu,addr,val,cond,interval,timeout) global() argument
[all...]
H A Da6xx_gpu.c25 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
515 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_set_hwcg() local
536 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, in a6xx_set_hwcg()
538 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, in a6xx_set_hwcg()
540 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, in a6xx_set_hwcg()
570 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); in a6xx_set_hwcg()
577 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); in a6xx_set_hwcg()
1068 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in hw_init() local
1446 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_recover() local
2067 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_pm_resume() local
2145 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_pm_suspend() local
[all...]
H A Da6xx_gpu.h85 struct a6xx_gmu gmu; member
247 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
249 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
251 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
252 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
H A Da6xx_gpu_state.c155 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu)) in a6xx_crashdumper_run()
1181 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers() local
1201 val = gmu_read_rscc(gmu, offset); in _a6xx_get_gmu_registers()
1203 val = gmu_read(gmu, offset); in _a6xx_get_gmu_registers()
1237 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_get_gmu_registers()
1275 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_snapshot_gmu_hfi_history() local
1278 BUILD_BUG_ON(ARRAY_SIZE(gmu->queues) != ARRAY_SIZE(a6xx_state->hfi_queue_history)); in a6xx_snapshot_gmu_hfi_history()
1280 for (i = 0; i < ARRAY_SIZE(gmu in a6xx_snapshot_gmu_hfi_history()
[all...]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8992.dtsi31 gmu-sram@0 {
H A Dsm6350.dtsi1422 qcom,gmu = <&gmu>;
1506 gmu: gmu@3d6a000 { label
1507 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1511 reg-names = "gmu",
1518 "gmu";
1526 "gmu",
H A Dsar2130p.dtsi1713 qcom,gmu = <&gmu>;
1772 gmu: gmu@3d6a000 { label
1773 compatible = "qcom,adreno-gmu-621.0", "qcom,adreno-gmu";
1777 reg-names = "gmu", "rscc", "gmu_pdc";
1781 interrupt-names = "hfi", "gmu";
1790 "gmu",
H A Dsm8350.dtsi2049 qcom,gmu = <&gmu>;
2114 gmu: gmu@3d6a000 { label
2115 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
2120 reg-names = "gmu", "rscc", "gmu_pdc";
2124 interrupt-names = "hfi", "gmu";
2133 clock-names = "gmu",
H A Dsc8180x.dtsi2271 qcom,gmu = <&gmu>;
2316 gmu: gmu@2c6a000 { label
2317 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2322 reg-names = "gmu",
2328 interrupt-names = "hfi", "gmu";
2335 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
H A Dqcm2290.dtsi1500 "gmu",
1511 qcom,gmu = <&gmu_wrapper>;
1580 gmu_wrapper: gmu@596a000 {
1581 compatible = "qcom,adreno-gmu-wrapper";
1583 reg-names = "gmu";
H A Dsc7180.dtsi2172 qcom,gmu = <&gmu>;
2266 gmu: gmu@506a000 { label
2267 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupt-names = "hfi", "gmu";
2278 clock-names = "gmu", "cxo", "axi", "memnoc";
H A Dsm8150-mtp.dts353 &gmu {
H A Dsm8250-hdk.dts368 &gmu {
H A Dsm8150.dtsi2250 qcom,gmu = <&gmu>;
2303 gmu: gmu@2c6a000 { label
2304 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2309 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 interrupt-names = "hfi", "gmu";
2320 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
H A Dsm6115.dtsi1732 "gmu",
1740 qcom,gmu = <&gmu_wrapper>;
1806 gmu_wrapper: gmu@596a000 {
1807 compatible = "qcom,adreno-gmu-wrapper";
1809 reg-names = "gmu";
H A Dsdm845.dtsi4889 qcom,gmu = <&gmu>;
4966 gmu: gmu@506a000 { label
4967 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4972 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4976 interrupt-names = "hfi", "gmu";
4982 clock-names = "gmu", "cxo", "axi", "memnoc";
H A Dsc8280xp.dtsi2994 qcom,gmu = <&gmu>;
3054 gmu: gmu@3d6a000 { label
3055 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
3059 reg-names = "gmu", "rscc", "gmu_pdc";
3062 interrupt-names = "hfi", "gmu";
3070 clock-names = "gmu",
H A Dsm8150-hdk.dts374 &gmu {
H A Dsm8550.dtsi2450 qcom,gmu = <&gmu>;
2517 gmu: gmu@3d6a000 { label
2518 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
2522 reg-names = "gmu", "rscc", "gmu_pdc";
2526 interrupt-names = "hfi", "gmu";
2536 "gmu",
H A Dsm8250.dtsi2939 qcom,gmu = <&gmu>;
2998 gmu: gmu@3d6a000 { label
2999 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
3005 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
3009 interrupt-names = "hfi", "gmu";
3016 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
H A Dsm8250-xiaomi-pipa.dts473 &gmu {
H A Dsc7280.dtsi2864 qcom,gmu = <&gmu>;
2947 gmu: gmu@3d6a000 { label
2948 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2952 reg-names = "gmu", "rscc", "gmu_pdc";
2955 interrupt-names = "hfi", "gmu";
2963 clock-names = "gmu",
/linux/drivers/gpu/drm/ci/xfails/
H A Dmsm-sm8350-hdk-skips.txt30 # [ 200.950227] platform 3d6a000.gmu: [drm:a6xx_hfi_send_msg.constprop.0] *ERROR* Message HFI_H2F_MSG_GX_BW_PERF_VOTE id 25 timed out waiting for response
35 # [ 204.213387] platform 3d6a000.gmu: GMU watchdog expired

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