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Searched refs:dspcntr (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Di9xx_plane.c164 u32 dspcntr; in i9xx_plane_ctl() local
166 dspcntr = DISP_ENABLE; in i9xx_plane_ctl()
170 dspcntr |= DISP_TRICKLE_FEED_DISABLE; in i9xx_plane_ctl()
174 dspcntr |= DISP_FORMAT_8BPP; in i9xx_plane_ctl()
177 dspcntr |= DISP_FORMAT_BGRX555; in i9xx_plane_ctl()
180 dspcntr |= DISP_FORMAT_BGRA555; in i9xx_plane_ctl()
183 dspcntr |= DISP_FORMAT_BGRX565; in i9xx_plane_ctl()
186 dspcntr |= DISP_FORMAT_BGRX888; in i9xx_plane_ctl()
189 dspcntr |= DISP_FORMAT_RGBX888; in i9xx_plane_ctl()
192 dspcntr | in i9xx_plane_ctl()
367 u32 dspcntr = 0; i9xx_plane_ctl_crtc() local
466 u32 dspcntr, dspaddr_offset, linear_offset; i9xx_plane_update_arm() local
542 u32 dspcntr; i9xx_plane_disable_arm() local
606 u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); g4x_primary_async_flip() local
913 u32 dspcntr; i9xx_disable_tiling() local
[all...]
/linux/drivers/gpu/drm/gma500/
H A Doaktrail_crtc.c373 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in oaktrail_crtc_mode_set() local
491 dspcntr = REG_READ(map->cntr); in oaktrail_crtc_mode_set()
492 dspcntr |= DISPPLANE_GAMMA_ENABLE; in oaktrail_crtc_mode_set()
495 dspcntr |= DISPPLANE_SEL_PIPE_A; in oaktrail_crtc_mode_set()
497 dspcntr |= DISPPLANE_SEL_PIPE_B; in oaktrail_crtc_mode_set()
583 REG_WRITE_WITH_AUX(map->cntr, dspcntr, i); in oaktrail_crtc_mode_set()
603 u32 dspcntr; in oaktrail_pipe_set_base() local
620 dspcntr = REG_READ(map->cntr); in oaktrail_pipe_set_base()
621 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; in oaktrail_pipe_set_base()
625 dspcntr | in oaktrail_pipe_set_base()
[all...]
H A Dpsb_intel_display.c107 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
200 dspcntr = DISPPLANE_GAMMA_ENABLE; in psb_intel_crtc_mode_set()
203 dspcntr |= DISPPLANE_SEL_PIPE_A; in psb_intel_crtc_mode_set()
205 dspcntr |= DISPPLANE_SEL_PIPE_B; in psb_intel_crtc_mode_set()
207 dspcntr |= DISPLAY_PLANE_ENABLE; in psb_intel_crtc_mode_set()
292 REG_WRITE(map->cntr, dspcntr); in psb_intel_crtc_mode_set()
H A Dgma_display.c69 u32 dspcntr; in gma_pipe_set_base() local
93 dspcntr = REG_READ(map->cntr); in gma_pipe_set_base()
94 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; in gma_pipe_set_base()
98 dspcntr |= DISPPLANE_8BPP; in gma_pipe_set_base()
102 dspcntr |= DISPPLANE_15_16BPP; in gma_pipe_set_base()
104 dspcntr |= DISPPLANE_16BPP; in gma_pipe_set_base()
108 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; in gma_pipe_set_base()
115 REG_WRITE(map->cntr, dspcntr); in gma_pipe_set_base()
H A Doaktrail_hdmi.c285 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
359 dspcntr = REG_READ(dspcntr_reg); in oaktrail_crtc_hdmi_mode_set()
360 dspcntr |= DISPPLANE_GAMMA_ENABLE; in oaktrail_crtc_hdmi_mode_set()
361 dspcntr |= DISPPLANE_SEL_PIPE_B; in oaktrail_crtc_hdmi_mode_set()
362 dspcntr |= DISPLAY_PLANE_ENABLE; in oaktrail_crtc_hdmi_mode_set()
375 REG_WRITE(dspcntr_reg, dspcntr); in oaktrail_crtc_hdmi_mode_set()
H A Dcdv_intel_display.c584 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
712 dspcntr = DISPPLANE_GAMMA_ENABLE; in cdv_intel_crtc_mode_set()
715 dspcntr |= DISPPLANE_SEL_PIPE_A; in cdv_intel_crtc_mode_set()
717 dspcntr |= DISPPLANE_SEL_PIPE_B; in cdv_intel_crtc_mode_set()
719 dspcntr |= DISPLAY_PLANE_ENABLE; in cdv_intel_crtc_mode_set()
808 REG_WRITE(map->cntr, dspcntr); in cdv_intel_crtc_mode_set()
H A Dpsb_drv.h521 u32 dspcntr[3]; member