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Searched refs:dpp_base (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp_cm.c92 struct dpp *dpp_base, in dpp401_set_cursor_attributes() argument
95 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_set_cursor_attributes()
106 if (!dpp_base->cursor_offload) in dpp401_set_cursor_attributes()
115 if (!dpp_base->cursor_offload) { in dpp401_set_cursor_attributes()
123 dpp_base->att.cur0_ctl.bits.expansion_mode = 0; in dpp401_set_cursor_attributes()
124 dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en; in dpp401_set_cursor_attributes()
125 dpp_base->att.cur0_ctl.bits.mode = color_format; in dpp401_set_cursor_attributes()
129 struct dpp *dpp_base, in dpp401_set_cursor_position() argument
135 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_set_cursor_position()
138 if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) { in dpp401_set_cursor_position()
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H A Ddcn401_dpp.c45 void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp401_read_state() argument
47 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp401_read_state()
56 struct dpp *dpp_base, in dpp401_dpp_setup() argument
63 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_dpp_setup()
214 dpp3_program_post_csc(dpp_base, color_space, select, in dpp401_dpp_setup()
217 dpp3_program_post_csc(dpp_base, color_space, select, NULL); in dpp401_dpp_setup()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c51 struct dpp *dpp_base) in dpp2_enable_cm_block() argument
53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block()
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse() argument
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse()
86 struct dpp *dpp_base, in dpp2_program_degamma_lut() argument
93 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_program_degamma_lut()
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl() argument
122 dpp1_power_on_degamma_lut(dpp_base, true); in dpp2_set_degamma_pwl()
123 dpp2_enable_cm_block(dpp_base); in dpp2_set_degamma_pwl()
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H A Ddcn20_dpp.c51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state() argument
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state()
78 struct dpp *dpp_base, in dpp2_power_on_obuf() argument
81 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf()
93 struct dpp *dpp_base, in dpp2_dummy_program_input_lut() argument
98 struct dpp *dpp_base, in dpp2_cnv_setup() argument
105 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup()
244 dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry); in dpp2_cnv_setup()
246 dpp2_program_input_csc(dpp_base, color_space, select, NULL); in dpp2_cnv_setup()
255 dpp2_power_on_obuf(dpp_base, true); in dpp2_cnv_setup()
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H A Ddcn20_dpp.h709 void dpp20_read_state(struct dpp *dpp_base,
713 struct dpp *dpp_base,
717 struct dpp *dpp_base,
721 struct dpp *dpp_base,
725 struct dpp *dpp_base,
731 struct dpp *dpp_base, const struct pwl_params *params);
734 struct dpp *dpp_base,
738 struct dpp *dpp_base,
742 struct dpp *dpp_base,
759 struct dpp *dpp_base,
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp30_read_state() argument
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_read_state()
87 void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state) in dpp30_read_reg_state() argument
89 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_read_reg_state()
105 struct dpp *dpp_base, in dpp3_program_post_csc() argument
110 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_post_csc()
178 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr) in dpp3_set_pre_degam() argument
180 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_set_pre_degam()
221 struct dpp *dpp_base, in dpp3_cnv_setup() argument
228 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_cnv_setup()
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H A Ddcn30_dpp_cm.c44 struct dpp *dpp_base) in dpp3_enable_cm_block() argument
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block()
51 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp3_enable_cm_block()
57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current() argument
62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current()
78 struct dpp *dpp_base, in dpp3_program_gammcor_lut() argument
84 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_gammcor_lut()
127 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut() argument
130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_power_on_gamcor_lut()
132 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { in dpp3_power_on_gamcor_lut()
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H A Ddcn30_dpp.h588 struct dpp *dpp_base, const struct pwl_params *params);
591 struct dpp *dpp_base,
594 void dpp30_read_state(struct dpp *dpp_base,
597 void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state);
605 struct dpp *dpp_base,
613 struct dpp *dpp_base,
617 struct dpp *dpp_base,
621 struct dpp *dpp_base,
624 void dpp3_set_pre_degam(struct dpp *dpp_base,
628 struct dpp *dpp_base,
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp.c94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state() argument
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_read_state()
188 void dpp_reset(struct dpp *dpp_base) in dpp_reset() argument
190 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_reset()
197 memset(&dpp_base->pos, 0, sizeof(dpp_base->pos)); in dpp_reset()
198 memset(&dpp_base->att, 0, sizeof(dpp_base->att)); in dpp_reset()
203 dpp_base->cursor_offload = false; in dpp_reset()
209 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) in dpp1_cm_set_regamma_pwl() argument
211 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_regamma_pwl()
229 dpp1_cm_power_on_regamma_lut(dpp_base, true); in dpp1_cm_set_regamma_pwl()
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H A Ddcn10_dpp_cm.c161 struct dpp *dpp_base, in dpp1_cm_set_gamut_remap() argument
164 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_gamut_remap()
233 void dpp1_cm_get_gamut_remap(struct dpp *dpp_base, in dpp1_cm_get_gamut_remap() argument
236 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_get_gamut_remap()
308 struct dpp *dpp_base, in dpp1_cm_set_output_csc_default() argument
311 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_default()
378 struct dpp *dpp_base, in dpp1_cm_set_output_csc_adjustment() argument
381 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_adjustment()
386 void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, in dpp1_cm_power_on_regamma_lut() argument
389 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_power_on_regamma_lut()
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H A Ddcn10_dpp_dscl.c124 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode() argument
130 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_get_dscl_mode()
158 struct dpp *dpp_base, in dpp1_power_on_dscl() argument
161 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl()
613 void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base, in dpp1_dscl_set_scaler_manual_scale() argument
617 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_dscl_set_scaler_manual_scale()
619 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); in dpp1_dscl_set_scaler_manual_scale()
630 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) { in dpp1_dscl_set_scaler_manual_scale()
632 dpp1_power_on_dscl(dpp_base, true); in dpp1_dscl_set_scaler_manual_scale()
659 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) in dpp1_dscl_set_scaler_manual_scale()
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddpp.h227 struct dpp *dpp_base, const struct pwl_params *params);
229 void (*dpp_set_pre_degam)(struct dpp *dpp_base,
232 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
236 struct dpp *dpp_base,
301 struct dpp *dpp_base,
305 struct dpp *dpp_base,
308 void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
312 struct dpp *dpp_base,
319 void (*dpp_full_bypass)(struct dpp *dpp_base);
322 struct dpp *dpp_base,
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/
H A Ddcn35_dpp.c41 struct dpp *dpp_base, in dpp35_dppclk_control() argument
45 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp35_dppclk_control()
71 struct dpp *dpp_base, in dpp35_program_bias_and_scale_fcnv() argument
74 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp35_program_bias_and_scale_fcnv()
H A Ddcn35_dpp.h53 struct dpp *dpp_base,
64 void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c237 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut() local
245 &plane_state->blend_tf, &dpp_base->regamma_params, false); in dcn30_set_blend_lut()
249 blend_lut = &dpp_base->regamma_params; in dcn30_set_blend_lut()
251 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn30_set_blend_lut()
259 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut() local
274 &dpp_base->shaper_params, true); in dcn30_set_mpc_shaper_3dlut()
275 shaper_lut = &dpp_base->shaper_params; in dcn30_set_mpc_shaper_3dlut()
321 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func() local
326 if (dpp_base == NULL || plane_state == NULL) in dcn30_set_input_transfer_func()
334 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn30_set_input_transfer_func()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c1057 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_blend_lut() local
1066 &dpp_base->regamma_params, false); in dcn20_set_blend_lut()
1067 blend_lut = &dpp_base->regamma_params; in dcn20_set_blend_lut()
1069 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn20_set_blend_lut()
1077 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_shaper_3dlut() local
1086 &dpp_base->shaper_params, true); in dcn20_set_shaper_3dlut()
1087 shaper_lut = &dpp_base->shaper_params; in dcn20_set_shaper_3dlut()
1090 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); in dcn20_set_shaper_3dlut()
1092 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, in dcn20_set_shaper_3dlut()
1095 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); in dcn20_set_shaper_3dlut()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c45 struct dpp *dpp_base, in dpp201_cnv_setup() argument
52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup()
177 dpp1_program_input_csc(dpp_base, color_space, select, NULL); in dpp201_cnv_setup()
185 dpp2_power_on_obuf(dpp_base, true); in dpp201_cnv_setup()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c449 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mpc_shaper_3dlut() local
463 &dpp_base->shaper_params, true); in dcn32_set_mpc_shaper_3dlut()
464 shaper_lut = &dpp_base->shaper_params; in dcn32_set_mpc_shaper_3dlut()
486 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mcm_luts() local
498 &dpp_base->regamma_params, false); in dcn32_set_mcm_luts()
502 lut_params = &dpp_base->regamma_params; in dcn32_set_mcm_luts()
514 &dpp_base->shaper_params, true); in dcn32_set_mcm_luts()
515 lut_params = rval ? &dpp_base->shaper_params : NULL; in dcn32_set_mcm_luts()
535 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_input_transfer_func() local
549 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn32_set_input_transfer_func()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c2035 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn10_set_input_transfer_func() local
2039 if (dpp_base == NULL) in dcn10_set_input_transfer_func()
2044 if (!dpp_base->ctx->dc->debug.always_use_regamma in dcn10_set_input_transfer_func()
2047 dpp_base->funcs->dpp_program_input_lut(dpp_base, &plane_state->gamma_correction); in dcn10_set_input_transfer_func()
2052 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB); in dcn10_set_input_transfer_func()
2055 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC); in dcn10_set_input_transfer_func()
2058 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
2061 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); in dcn10_set_input_transfer_func()
2062 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); in dcn10_set_input_transfer_func()
2063 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); in dcn10_set_input_transfer_func()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c418 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_populate_mcm_luts() local
446 &dpp_base->regamma_params, false); in dcn401_populate_mcm_luts()
447 m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; in dcn401_populate_mcm_luts()
466 &dpp_base->regamma_params, true); in dcn401_populate_mcm_luts()
467 m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; in dcn401_populate_mcm_luts()
622 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_set_mcm_luts() local
643 &dpp_base->regamma_params, false); in dcn401_set_mcm_luts()
644 lut_params = rval ? &dpp_base->regamma_params : NULL; in dcn401_set_mcm_luts()
656 &dpp_base->shaper_params, true); in dcn401_set_mcm_luts()
657 lut_params = rval ? &dpp_base->shaper_params : NULL; in dcn401_set_mcm_luts()