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Searched refs:dml2_options (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c356 dc->dml2_options.bbox_overrides.clks_table.num_states = in dcn35_update_bw_bounding_box_fpu()
358 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = in dcn35_update_bw_bounding_box_fpu()
360 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz = in dcn35_update_bw_bounding_box_fpu()
362 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz = in dcn35_update_bw_bounding_box_fpu()
364 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz = in dcn35_update_bw_bounding_box_fpu()
366 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz = in dcn35_update_bw_bounding_box_fpu()
368 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz = in dcn35_update_bw_bounding_box_fpu()
371 …dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_sp… in dcn35_update_bw_bounding_box_fpu()
372 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz = in dcn35_update_bw_bounding_box_fpu()
374 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn35_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c390 dc->dml2_options.bbox_overrides.clks_table.num_states = in dcn351_update_bw_bounding_box_fpu()
392 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = in dcn351_update_bw_bounding_box_fpu()
394 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz = in dcn351_update_bw_bounding_box_fpu()
396 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz = in dcn351_update_bw_bounding_box_fpu()
398 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz = in dcn351_update_bw_bounding_box_fpu()
400 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz = in dcn351_update_bw_bounding_box_fpu()
402 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz = in dcn351_update_bw_bounding_box_fpu()
404 …dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_sp… in dcn351_update_bw_bounding_box_fpu()
405 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz = in dcn351_update_bw_bounding_box_fpu()
407 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn351_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c619 dc->dml2_options.bbox_overrides.sr_exit_latency_us = in dcn321_update_bw_bounding_box_fpu()
626 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = in dcn321_update_bw_bounding_box_fpu()
634 dc->dml2_options.bbox_overrides.urgent_latency_us = in dcn321_update_bw_bounding_box_fpu()
641 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
649 dc->dml2_options.bbox_overrides.fclk_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
667 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
672 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = in dcn321_update_bw_bounding_box_fpu()
677 dc->dml2_options.bbox_overrides.sr_exit_latency_us = in dcn321_update_bw_bounding_box_fpu()
685 dc->dml2_options.bbox_overrides.dram_num_chan = in dcn321_update_bw_bounding_box_fpu()
692 dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = in dcn321_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c1622 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); in dcn321_update_bw_bounding_box()
2060 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn321_resource_construct()
2061 dc->dml2_options.use_native_soc_bb_construction = true; in dcn321_resource_construct()
2062 dc->dml2_options.minimize_dispclk_using_odm = true; in dcn321_resource_construct()
2064 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); in dcn321_resource_construct()
2065 …dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_supp… in dcn321_resource_construct()
2066 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; in dcn321_resource_construct()
2067 …dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate… in dcn321_resource_construct()
2069 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us; in dcn321_resource_construct()
2070 …dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_m… in dcn321_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c1659 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); in dcn401_update_bw_bounding_box()
2262 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn401_resource_construct()
2263 dc->dml2_options.use_native_soc_bb_construction = true; in dcn401_resource_construct()
2264 dc->dml2_options.minimize_dispclk_using_odm = true; in dcn401_resource_construct()
2265 dc->dml2_options.map_dc_pipes_with_callbacks = true; in dcn401_resource_construct()
2266 dc->dml2_options.force_tdlut_enable = true; in dcn401_resource_construct()
2268 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); in dcn401_resource_construct()
2269 …dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_supp… in dcn401_resource_construct()
2270 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; in dcn401_resource_construct()
2271 …dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate… in dcn401_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c2107 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); in dcn32_update_bw_bounding_box()
2566 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn32_resource_construct()
2567 dc->dml2_options.use_native_soc_bb_construction = true; in dcn32_resource_construct()
2568 dc->dml2_options.minimize_dispclk_using_odm = true; in dcn32_resource_construct()
2570 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); in dcn32_resource_construct()
2571 …dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_supp… in dcn32_resource_construct()
2572 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; in dcn32_resource_construct()
2573 …dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate… in dcn32_resource_construct()
2575 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us; in dcn32_resource_construct()
2576 …dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_m… in dcn32_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c5638 …resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options) in resource_init_common_dml2_callbacks() argument
5640 dml2_options->callbacks.dc = dc; in resource_init_common_dml2_callbacks()
5641 dml2_options->callbacks.build_scaling_params = &resource_build_scaling_params; in resource_init_common_dml2_callbacks()
5642 dml2_options->callbacks.build_test_pattern_params = &resource_build_test_pattern_params; in resource_init_common_dml2_callbacks()
5643 …dml2_options->callbacks.acquire_secondary_pipe_for_mpc_odm = &dc_resource_acquire_secondary_pipe_f… in resource_init_common_dml2_callbacks()
5644 …dml2_options->callbacks.update_pipes_for_stream_with_slice_count = &resource_update_pipes_for_stre… in resource_init_common_dml2_callbacks()
5645 …dml2_options->callbacks.update_pipes_for_plane_with_slice_count = &resource_update_pipes_for_plane… in resource_init_common_dml2_callbacks()
5646 dml2_options->callbacks.get_mpc_slice_index = &resource_get_mpc_slice_index; in resource_init_common_dml2_callbacks()
5647 dml2_options->callbacks.get_mpc_slice_count = &resource_get_mpc_slice_count; in resource_init_common_dml2_callbacks()
5648 dml2_options->callbacks.get_odm_slice_index = &resource_get_odm_slice_index; in resource_init_common_dml2_callbacks()
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H A Ddc_vm_helper.c50 dc->dml2_options.gpuvm_enable = true; in dc_setup_system_context()
H A Ddc_state.c209 if (!dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2)) { in dc_state_create()
H A Ddc.c1106 dc->dml2_options.bb_from_dmub = init_params->bb_from_dmub; in dc_construct()
1108 dc->dml2_options.bb_from_dmub = NULL; in dc_construct()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c3061 dc->dml2_options.bbox_overrides.sr_exit_latency_us = in dcn32_update_bw_bounding_box_fpu()
3068 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = in dcn32_update_bw_bounding_box_fpu()
3076 dc->dml2_options.bbox_overrides.urgent_latency_us = in dcn32_update_bw_bounding_box_fpu()
3083 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn32_update_bw_bounding_box_fpu()
3091 dc->dml2_options.bbox_overrides.fclk_change_latency_us = in dcn32_update_bw_bounding_box_fpu()
3109 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn32_update_bw_bounding_box_fpu()
3114 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = in dcn32_update_bw_bounding_box_fpu()
3119 dc->dml2_options.bbox_overrides.sr_exit_latency_us = in dcn32_update_bw_bounding_box_fpu()
3127 dc->dml2_options.bbox_overrides.dram_num_chan = in dcn32_update_bw_bounding_box_fpu()
3134 dc->dml2_options.bbox_overrides.dram_chanel_width_bytes = in dcn32_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c2194 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn351_resource_construct()
2195 dc->dml2_options.use_native_soc_bb_construction = true; in dcn351_resource_construct()
2196 dc->dml2_options.minimize_dispclk_using_odm = false; in dcn351_resource_construct()
2198 dc->dml2_options.minimize_dispclk_using_odm = true; in dcn351_resource_construct()
2199 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; in dcn351_resource_construct()
2201 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); in dcn351_resource_construct()
2202 …dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_supp… in dcn351_resource_construct()
2204 dc->dml2_options.max_segments_per_hubp = 24; in dcn351_resource_construct()
2205 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/ in dcn351_resource_construct()
2206 dc->dml2_options.override_det_buffer_size_kbytes = true; in dcn351_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c2200 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn36_resource_construct()
2201 dc->dml2_options.use_native_soc_bb_construction = true; in dcn36_resource_construct()
2202 dc->dml2_options.minimize_dispclk_using_odm = false; in dcn36_resource_construct()
2204 dc->dml2_options.minimize_dispclk_using_odm = true; in dcn36_resource_construct()
2205 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; in dcn36_resource_construct()
2207 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); in dcn36_resource_construct()
2208 …dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_supp… in dcn36_resource_construct()
2210 dc->dml2_options.max_segments_per_hubp = 24; in dcn36_resource_construct()
2211 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/ in dcn36_resource_construct()
2212 dc->dml2_options.override_det_buffer_size_kbytes = true; in dcn36_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c2221 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; in dcn35_resource_construct()
2222 dc->dml2_options.use_native_soc_bb_construction = true; in dcn35_resource_construct()
2223 dc->dml2_options.minimize_dispclk_using_odm = false; in dcn35_resource_construct()
2225 dc->dml2_options.minimize_dispclk_using_odm = true; in dcn35_resource_construct()
2226 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; in dcn35_resource_construct()
2228 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); in dcn35_resource_construct()
2229 …dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_supp… in dcn35_resource_construct()
2231 dc->dml2_options.max_segments_per_hubp = 24; in dcn35_resource_construct()
2232 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/ in dcn35_resource_construct()
2233 dc->dml2_options.override_det_buffer_size_kbytes = true; in dcn35_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dresource.h650 …esource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options);
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h1824 struct dml2_configuration_options dml2_options; member