Home
last modified time | relevance | path

Searched refs:dispc (Results 1 – 25 of 43) sorted by relevance

12

/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddispc.c50 #define REG_GET(dispc, idx, start, end) \ argument
51 FLD_GET(dispc_read_reg(dispc, idx), start, end)
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
54 dispc_write_reg(dispc, idx, \
55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
102 int (*calc_scaling)(struct dispc_device *dispc,
344 static unsigned long dispc_fclk_rate(struct dispc_device *dispc);
345 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc);
346 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
348 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
[all …]
H A Ddss.h259 struct dispc_device *dispc; member
389 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);
391 int dispc_runtime_get(struct dispc_device *dispc);
392 void dispc_runtime_put(struct dispc_device *dispc);
394 int dispc_get_num_ovls(struct dispc_device *dispc);
395 int dispc_get_num_mgrs(struct dispc_device *dispc);
397 const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc,
400 void dispc_ovl_get_max_size(struct dispc_device *dispc, u16 *width, u16 *height);
401 bool dispc_ovl_color_mode_supported(struct dispc_device *dispc,
403 enum omap_overlay_caps dispc_ovl_get_caps(struct dispc_device *dispc, enum omap_plane_id plane);
[all …]
H A Ddpi.c179 static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, in dpi_calc_hsdiv_cb() argument
185 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; in dpi_calc_hsdiv_cb()
187 return dispc_div_calc(ctx->dpi->dss->dispc, dispc, in dpi_calc_hsdiv_cb()
215 return dispc_div_calc(ctx->dpi->dss->dispc, fck, in dpi_calc_dss_cb()
496 r = dispc_runtime_get(dpi->dss->dispc); in dpi_bridge_enable()
530 dispc_runtime_put(dpi->dss->dispc); in dpi_bridge_enable()
548 dispc_runtime_put(dpi->dss->dispc); in dpi_bridge_disable()
H A Dsdi.c69 return dispc_div_calc(ctx->sdi->dss->dispc, fck, in dpi_calc_dss_cb()
211 r = dispc_runtime_get(sdi->dss->dispc); in sdi_bridge_enable()
238 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel, in sdi_bridge_enable()
258 dispc_runtime_put(sdi->dss->dispc); in sdi_bridge_enable()
271 dispc_runtime_put(sdi->dss->dispc); in sdi_bridge_disable()
H A Ddss.c267 dispc_pck_free_enable(dss->dispc, 1); in dss_sdi_enable()
297 dispc_lcd_enable_signal(dss->dispc, 1); in dss_sdi_enable()
311 dispc_lcd_enable_signal(dss->dispc, 0); in dss_sdi_enable()
316 dispc_pck_free_enable(dss->dispc, 0); in dss_sdi_enable()
323 dispc_lcd_enable_signal(dss->dispc, 0); in dss_sdi_disable()
325 dispc_pck_free_enable(dss->dispc, 0); in dss_sdi_disable()
386 dispc_dump_clocks(dss->dispc, s); in dss_debug_dump_clocks()
/linux/drivers/gpu/drm/tidss/
H A Dtidss_dispc.c482 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val) in dispc_write() argument
484 iowrite32(val, dispc->base_common + reg); in dispc_write()
487 static u32 dispc_read(struct dispc_device *dispc, u16 reg) in dispc_read() argument
489 return ioread32(dispc->base_common + reg); in dispc_read()
493 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) in dispc_vid_write() argument
495 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
500 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) in dispc_vid_read() argument
502 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
507 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport, in dispc_ovr_write() argument
510 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_write()
[all …]
H A Dtidss_dispc.h109 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask);
110 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc);
112 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
114 void dispc_ovr_enable_layer(struct dispc_device *dispc,
117 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
119 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport);
120 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport);
121 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport);
122 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport);
123 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport);
[all …]
H A Dtidss_crtc.c38 busy = dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_finish_page_flip()
92 struct dispc_device *dispc = tidss->dispc; in tidss_crtc_atomic_check() local
103 ok = dispc_vp_mode_valid(dispc, hw_videoport, mode); in tidss_crtc_atomic_check()
113 return dispc_vp_bus_check(dispc, hw_videoport, crtc_state); in tidss_crtc_atomic_check()
154 dispc_ovr_set_plane(tidss->dispc, tplane->hw_plane_id, in tidss_crtc_position_planes()
159 dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer, in tidss_crtc_position_planes()
187 if (WARN_ON(dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport))) in tidss_crtc_atomic_flush()
195 dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, false); in tidss_crtc_atomic_flush()
203 dispc_vp_go(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_atomic_flush()
229 r = dispc_vp_set_clk_rate(tidss->dispc, tcrtc->hw_videoport, in tidss_crtc_atomic_enable()
[all …]
H A Dtidss_drv.c55 return dispc_runtime_suspend(tidss->dispc); in tidss_pm_runtime_suspend()
63 r = dispc_runtime_resume(tidss->dispc); in tidss_pm_runtime_resume()
149 dispc_runtime_resume(tidss->dispc); in tidss_probe()
201 dispc_runtime_suspend(tidss->dispc); in tidss_probe()
225 dispc_runtime_suspend(tidss->dispc); in tidss_remove()
H A Dtidss_plane.c107 ret = dispc_plane_check(tidss->dispc, hw_plane, new_plane_state, in tidss_plane_atomic_check()
126 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); in tidss_plane_atomic_update()
132 dispc_plane_setup(tidss->dispc, tplane->hw_plane_id, new_state, hw_videoport); in tidss_plane_atomic_update()
142 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true); in tidss_plane_atomic_enable()
152 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); in tidss_plane_atomic_disable()
H A Dtidss_irq.c22 dispc_set_irqenable(tidss->dispc, tidss->irq_mask); in tidss_irq_update()
63 irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc); in tidss_irq_handler()
H A Dtidss_drv.h26 struct dispc_device *dispc; member
/linux/drivers/gpu/drm/omapdrm/
H A Domap_irq.c33 dispc_write_irqenable(priv->dispc, irqmask); in omap_irq_update()
87 dispc_mgr_get_framedone_irq(priv->dispc, channel); in omap_irq_enable_framedone()
124 priv->irq_mask |= dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_enable_vblank()
150 priv->irq_mask &= ~dispc_mgr_get_vsync_irq(priv->dispc, in omap_irq_disable_vblank()
215 irqstatus = dispc_read_irqstatus(priv->dispc); in omap_irq_handler()
216 dispc_clear_irqstatus(priv->dispc, irqstatus); in omap_irq_handler()
217 dispc_read_irqstatus(priv->dispc); /* flush posted write */ in omap_irq_handler()
225 if (irqstatus & dispc_mgr_get_vsync_irq(priv->dispc, channel)) { in omap_irq_handler()
230 if (irqstatus & dispc_mgr_get_sync_lost_irq(priv->dispc, channel)) in omap_irq_handler()
233 if (irqstatus & dispc_mgr_get_framedone_irq(priv->dispc, channel)) in omap_irq_handler()
[all …]
H A Domap_plane.c141 ret = dispc_ovl_setup(priv->dispc, ovl_id, &info, in omap_plane_atomic_update()
147 dispc_ovl_enable(priv->dispc, ovl_id, false); in omap_plane_atomic_update()
151 dispc_ovl_enable(priv->dispc, ovl_id, true); in omap_plane_atomic_update()
154 ret = dispc_ovl_setup(priv->dispc, r_ovl_id, &r_info, in omap_plane_atomic_update()
160 dispc_ovl_enable(priv->dispc, r_ovl_id, false); in omap_plane_atomic_update()
161 dispc_ovl_enable(priv->dispc, ovl_id, false); in omap_plane_atomic_update()
165 dispc_ovl_enable(priv->dispc, r_ovl_id, true); in omap_plane_atomic_update()
225 dispc_ovl_get_max_size(priv->dispc, &width, &height); in omap_plane_atomic_check()
317 if (!dispc_ovl_color_mode_supported(priv->dispc, omap_state->overlay->id, in omap_plane_atomic_check()
507 const u32 *formats = dispc_ovl_get_color_modes(priv->dispc, omap_plane->id); in omap_plane_supports_yuv()
[all …]
H A Domap_crtc.c106 dispc_mgr_enable(priv->dispc, channel, true); in omap_crtc_dss_start_update()
131 dispc_mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled()
144 framedone_irq = dispc_mgr_get_framedone_irq(priv->dispc, in omap_crtc_set_enabled()
146 vsync_irq = dispc_mgr_get_vsync_irq(priv->dispc, channel); in omap_crtc_set_enabled()
166 dispc_mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled()
188 dispc_mgr_set_timings(priv->dispc, omap_crtc->channel, in omap_crtc_dss_enable()
222 dispc_mgr_set_lcd_config(priv->dispc, omap_crtc->channel, in omap_crtc_dss_set_lcd_config()
291 if (dispc_mgr_go_busy(priv->dispc, omap_crtc->channel)) { in omap_crtc_vblank_irq()
417 dispc_mgr_setup(priv->dispc, omap_crtc->channel, &info); in omap_crtc_write_crtc_properties()
458 dispc_runtime_get(priv->dispc); in omap_crtc_atomic_enable()
[all …]
H A Domap_overlay.c51 if (!dispc_ovl_color_mode_supported(priv->dispc, in omap_plane_find_free_overlay()
148 dispc_ovl_enable(priv->dispc, overlay->id, false); in omap_overlay_update_state()
179 u32 num_overlays = dispc_get_num_ovls(priv->dispc); in omap_hwoverlays_init()
186 caps = dispc_ovl_get_caps(priv->dispc, hw_plane_ids[i]); in omap_hwoverlays_init()
H A Domap_drv.c73 dispc_runtime_get(priv->dispc); in omap_atomic_commit_tail()
117 dispc_runtime_put(priv->dispc); in omap_atomic_commit_tail()
367 unsigned int num_planes = dispc_get_num_ovls(priv->dispc); in omap_modeset_init_properties()
394 int num_ovls = dispc_get_num_ovls(priv->dispc); in omap_modeset_init()
395 int num_mgrs = dispc_get_num_mgrs(priv->dispc); in omap_modeset_init()
689 priv->dispc = dispc_get_dispc(priv->dss); in omapdrm_init()
705 priv->max_bandwidth = dispc_get_memory_bandwidth_limit(priv->dispc); in omapdrm_init()
H A Domap_drv.h64 struct dispc_device *dispc; member
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddispc.c127 } dispc; variable
253 __raw_writel(val, dispc.base + idx); in dispc_write_reg()
258 return __raw_readl(dispc.base + idx); in dispc_read_reg()
274 spin_lock_irqsave(&dispc.control_lock, flags); in mgr_fld_write()
279 spin_unlock_irqrestore(&dispc.control_lock, flags); in mgr_fld_write()
283 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
285 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
389 dispc.ctx_valid = true; in dispc_save_context()
400 if (!dispc.ctx_valid) in dispc_restore_context()
522 r = pm_runtime_resume_and_get(&dispc.pdev->dev); in dispc_runtime_get()
[all …]
H A DMakefile5 omapdss-y := core.o dss.o dss_features.o dispc.o dispc_coefs.o display.o \
9 dispc-compat.o display-sysfs.o
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,omap2-dss.txt26 - compatible: "ti,omap2-dispc"
32 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,dra7-dss.txt43 - compatible: "ti,dra7-dispc"
51 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap3-dss.txt33 - compatible: "ti,omap3-dispc"
41 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap5-dss.txt32 - compatible: "ti,omap5-dispc"
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
H A Dti,omap4-dss.txt32 - compatible: "ti,omap4-dispc"
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit

12