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Searched refs:dcn_dccg (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c33 container_of(dccg, struct dcn_dccg, base)
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto()
81 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_get_dccg_ref_freq()
102 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_set_fifo_errdet_ovr_en()
111 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_otg_add_pixel()
123 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_otg_drop_pixel()
134 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_init()
150 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_refclk_setup()
159 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_is_s0i3_golden_init_wa_done()
166 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_allow_clock_gating()
[all …]
H A Ddcn20_dccg.h502 struct dcn_dccg { struct
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.c32 container_of(dccg, struct dcn_dccg, base)
140 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_dsc_clk_rcg()
173 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_symclk32_se_rcg()
212 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_symclk32_le_rcg()
239 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_physymclk_rcg()
276 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_symclk_fe_rcg()
324 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_symclk_be_rcg()
370 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_dtbclk_p_rcg()
396 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_dppclk_rcg()
429 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_dpstreamclk_rcg()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
H A Ddcn401_dccg.c42 container_of(dccg, struct dcn_dccg, base)
59 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dcn401_set_dppclk_enable()
80 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_update_dpp_dto()
112 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_wait_for_dentist_change_done()
126 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_get_pixel_rate_div()
164 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_set_pixel_rate_div()
218 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_set_dtbclk_p_src()
274 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_set_physymclk()
367 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_otg_add_pixel()
376 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_otg_drop_pixel()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
H A Ddcn32_dccg.c32 container_of(dccg, struct dcn_dccg, base)
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_trigger_dio_fifo_resync()
65 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_get_pixel_rate_div()
107 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_set_pixel_rate_div()
154 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_set_dtbclk_p_src()
209 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_set_dtbclk_dto()
282 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_set_dpstreamclk()
316 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_otg_add_pixel()
325 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_otg_drop_pixel()
363 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn); in dccg32_create()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c33 container_of(dccg, struct dcn_dccg, base)
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_update_dpp_dto()
85 struct dcn_dccg *dccg_dcn, in get_phy_mux_symclk()
100 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_enable_dpstreamclk()
132 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_disable_dpstreamclk()
179 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_enable_symclk32_se()
231 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_disable_symclk32_se()
282 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_enable_symclk32_le()
308 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_disable_symclk32_le()
333 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_set_symclk32_le_root_clock_gating()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
H A Ddcn314_dccg.c35 container_of(dccg, struct dcn_dccg, base)
52 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_trigger_dio_fifo_resync()
65 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_get_pixel_rate_div()
107 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_set_pixel_rate_div()
154 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_set_dtbclk_p_src()
210 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_set_dtbclk_dto()
256 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_set_dpstreamclk()
335 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_dpp_root_clock_control()
395 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn); in dccg314_create()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn30/
H A Ddcn30_dccg.c31 container_of(dccg, struct dcn_dccg, base)
65 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn); in dccg3_create()
90 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn); in dccg30_create()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
H A Ddcn21_dccg.c32 container_of(dccg, struct dcn_dccg, base)
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto()
138 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn); in dccg21_create()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/
H A Ddcn301_dccg.c31 container_of(dccg, struct dcn_dccg, base)
64 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn); in dccg301_create()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/
H A Ddcn201_dccg.c33 container_of(dccg, struct dcn_dccg, base)
73 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn); in dccg201_create()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c59 container_of(dccg, struct dcn_dccg, base)