1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DCN31_DCCG_H__ 27 #define __DCN31_DCCG_H__ 28 29 #include "dcn30/dcn30_dccg.h" 30 31 #define DCCG_REG_LIST_DCN31() \ 32 SR(DPPCLK_DTO_CTRL),\ 33 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ 34 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ 35 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\ 36 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\ 37 DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\ 38 SR(PHYASYMCLK_CLOCK_CNTL),\ 39 SR(PHYBSYMCLK_CLOCK_CNTL),\ 40 SR(PHYCSYMCLK_CLOCK_CNTL),\ 41 SR(PHYDSYMCLK_CLOCK_CNTL),\ 42 SR(PHYESYMCLK_CLOCK_CNTL),\ 43 SR(DPSTREAMCLK_CNTL),\ 44 SR(HDMISTREAMCLK_CNTL),\ 45 SR(SYMCLK32_SE_CNTL),\ 46 SR(SYMCLK32_LE_CNTL),\ 47 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ 48 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\ 49 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ 50 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\ 51 DCCG_SRII(MODULO, DTBCLK_DTO, 0),\ 52 DCCG_SRII(MODULO, DTBCLK_DTO, 1),\ 53 DCCG_SRII(MODULO, DTBCLK_DTO, 2),\ 54 DCCG_SRII(MODULO, DTBCLK_DTO, 3),\ 55 DCCG_SRII(PHASE, DTBCLK_DTO, 0),\ 56 DCCG_SRII(PHASE, DTBCLK_DTO, 1),\ 57 DCCG_SRII(PHASE, DTBCLK_DTO, 2),\ 58 DCCG_SRII(PHASE, DTBCLK_DTO, 3),\ 59 SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\ 60 SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\ 61 SR(DCCG_AUDIO_DTO_SOURCE),\ 62 SR(DENTIST_DISPCLK_CNTL),\ 63 SR(DSCCLK0_DTO_PARAM),\ 64 SR(DSCCLK1_DTO_PARAM),\ 65 SR(DSCCLK2_DTO_PARAM),\ 66 SR(DSCCLK_DTO_CTRL),\ 67 SR(DCCG_GATE_DISABLE_CNTL),\ 68 SR(DCCG_GATE_DISABLE_CNTL2),\ 69 SR(DCCG_GATE_DISABLE_CNTL3),\ 70 SR(HDMISTREAMCLK0_DTO_PARAM),\ 71 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ 72 SR(MICROSECOND_TIME_BASE_DIV) 73 74 75 #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \ 76 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ 77 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ 78 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ 79 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ 80 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\ 81 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\ 82 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\ 83 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\ 84 DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ 85 DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ 86 DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\ 87 DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\ 88 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\ 89 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\ 90 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ 91 DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\ 92 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\ 93 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\ 94 DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\ 95 DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\ 96 DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\ 97 DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\ 98 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE0_EN, mask_sh),\ 99 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE1_EN, mask_sh),\ 100 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE2_EN, mask_sh),\ 101 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE3_EN, mask_sh),\ 102 DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\ 103 DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_DTO_FORCE_DIS, mask_sh),\ 104 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\ 105 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\ 106 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\ 107 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\ 108 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\ 109 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\ 110 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\ 111 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\ 112 DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\ 113 DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\ 114 DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\ 115 DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\ 116 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\ 117 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\ 118 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\ 119 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\ 120 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\ 121 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\ 122 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\ 123 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\ 124 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\ 125 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\ 126 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\ 127 DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\ 128 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 0, mask_sh),\ 129 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\ 130 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\ 131 DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\ 132 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ 133 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ 134 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ 135 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ 136 DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ 137 DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ 138 DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh),\ 139 DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\ 140 DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\ 141 DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\ 142 DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\ 143 DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\ 144 DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\ 145 DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\ 146 DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\ 147 DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh),\ 148 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\ 149 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\ 150 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\ 151 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\ 152 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\ 153 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_ROOT_GATE_DISABLE, mask_sh),\ 154 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_GATE_DISABLE, mask_sh),\ 155 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\ 156 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\ 157 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\ 158 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\ 159 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\ 160 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\ 161 DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\ 162 DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh) 163 164 165 struct dccg *dccg31_create( 166 struct dc_context *ctx, 167 const struct dccg_registers *regs, 168 const struct dccg_shift *dccg_shift, 169 const struct dccg_mask *dccg_mask); 170 171 void dccg31_init(struct dccg *dccg); 172 173 void dccg31_enable_symclk32_se( 174 struct dccg *dccg, 175 int hpo_se_inst, 176 enum phyd32clk_clock_source phyd32clk); 177 178 void dccg31_disable_symclk32_se( 179 struct dccg *dccg, 180 int hpo_se_inst); 181 182 void dccg31_enable_symclk32_le( 183 struct dccg *dccg, 184 int hpo_le_inst, 185 enum phyd32clk_clock_source phyd32clk); 186 187 void dccg31_disable_symclk32_le( 188 struct dccg *dccg, 189 int hpo_le_inst); 190 191 void dccg31_set_symclk32_le_root_clock_gating( 192 struct dccg *dccg, 193 int hpo_le_inst, 194 bool enable); 195 196 void dccg31_set_physymclk( 197 struct dccg *dccg, 198 int phy_inst, 199 enum physymclk_clock_source clk_src, 200 bool force_enable); 201 202 void dccg31_set_audio_dtbclk_dto( 203 struct dccg *dccg, 204 const struct dtbclk_dto_params *params); 205 206 void dccg31_update_dpp_dto( 207 struct dccg *dccg, 208 int dpp_inst, 209 int req_dppclk); 210 211 void dccg31_get_dccg_ref_freq( 212 struct dccg *dccg, 213 unsigned int xtalin_freq_inKhz, 214 unsigned int *dccg_ref_freq_inKhz); 215 216 void dccg31_set_dpstreamclk( 217 struct dccg *dccg, 218 enum streamclk_source src, 219 int otg_inst, 220 int dp_hpo_inst); 221 222 void dccg31_set_dtbclk_dto( 223 struct dccg *dccg, 224 const struct dtbclk_dto_params *params); 225 226 void dccg31_otg_add_pixel( 227 struct dccg *dccg, 228 uint32_t otg_inst); 229 230 void dccg31_otg_drop_pixel( 231 struct dccg *dccg, 232 uint32_t otg_inst); 233 234 void dccg31_set_dispclk_change_mode( 235 struct dccg *dccg, 236 enum dentist_dispclk_change_mode change_mode); 237 238 void dccg31_disable_dscclk(struct dccg *dccg, int inst); 239 240 void dccg31_enable_dscclk(struct dccg *dccg, int inst); 241 242 void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state); 243 244 #endif //__DCN31_DCCG_H__ 245