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/linux/drivers/clk/renesas/
H A DMakefile5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
12 obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
13 obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
14 obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
15 obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
18 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g057.dtsi8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
67 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
78 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
89 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
100 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
256 clocks = <&cpg CPG_MOD 0x5>;
257 power-domains = <&cpg>;
258 resets = <&cpg 0x36>;
264 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>;
271 power-domains = <&cpg>;
[all …]
H A Dr9a07g043.dtsi8 #include <dt-bindings/clock/r9a07g043-cpg.h>
140 clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
155 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
156 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
159 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
162 power-domains = <&cpg>;
175 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
176 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
[all …]
H A Dr9a09g056.dtsi8 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
85 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>;
96 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>;
107 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>;
118 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>;
274 clocks = <&cpg CPG_MOD 0x5>;
275 power-domains = <&cpg>;
276 resets = <&cpg 0x36>;
282 clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>;
289 power-domains = <&cpg>;
[all …]
H A Dr9a09g047.dtsi8 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
67 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
78 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
89 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
100 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
251 clocks = <&cpg CPG_MOD 0x5>;
252 power-domains = <&cpg>;
253 resets = <&cpg 0x36>;
259 clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>;
266 power-domains = <&cpg>;
[all …]
H A Dr9a08g045.dtsi9 #include <dt-bindings/clock/r9a08g045-cpg.h>
70 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
111 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
113 power-domains = <&cpg>;
114 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
129 clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>;
131 power-domains = <&cpg>;
132 resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>;
147 clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>;
149 power-domains = <&cpg>;
[all …]
H A Dr9a07g044.dtsi9 #include <dt-bindings/clock/r9a07g044-cpg.h>
95 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
105 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
356 clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
357 resets = <&cpg R9A07G044_GPT_RST_C>;
358 power-domains = <&cpg>;
370 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
[all …]
H A Dr9a07g054.dtsi9 #include <dt-bindings/clock/r9a07g054-cpg.h>
95 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
105 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
356 clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
357 resets = <&cpg R9A07G054_GPT_RST_C>;
358 power-domains = <&cpg>;
370 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
[all …]
H A Dr9a09g011.dtsi9 #include <dt-bindings/clock/r9a09g011-cpg.h>
42 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
68 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
78 clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
79 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
80 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
81 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
83 resets = <&cpg R9A09G011_SDI0_IXRST>;
84 power-domains = <&cpg>;
94 clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
[all …]
H A Dhihope-rev4.dtsi96 clocks = <&cpg CPG_MOD 1005>,
97 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
98 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
99 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
100 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
101 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
102 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
103 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
104 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
105 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
[all …]
H A Dr8a774c0.dtsi8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
83 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
94 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
153 clocks = <&cpg CPG_MOD 402>;
155 resets = <&cpg 402>;
169 clocks = <&cpg CPG_MOD 912>;
171 resets = <&cpg 912>;
184 clocks = <&cpg CPG_MOD 911>;
186 resets = <&cpg 911>;
199 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77990.dtsi8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
84 clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
96 clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
168 clocks = <&cpg CPG_MOD 402>;
170 resets = <&cpg 402>;
178 clocks = <&cpg CPG_CORE R8A77990_CLK_OSC>;
180 resets = <&cpg 401>;
194 clocks = <&cpg CPG_MOD 912>;
196 resets = <&cpg 912>;
209 clocks = <&cpg CPG_MOD 911>;
[all …]
H A Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
101 clocks = <&cpg CPG_MOD 402>;
103 resets = <&cpg 402>;
111 clocks = <&cpg CPG_CORE R8A77995_CLK_OSC>;
113 resets = <&cpg 401>;
127 clocks = <&cpg CPG_MOD 912>;
129 resets = <&cpg 912>;
142 clocks = <&cpg CPG_MOD 911>;
144 resets = <&cpg 911>;
157 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77965.dtsi11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
105 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
117 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
198 clocks = <&cpg CPG_MOD 402>;
200 resets = <&cpg 402>;
208 clocks = <&cpg CPG_CORE R8A77965_CLK_OSC>;
210 resets = <&cpg 401>;
224 clocks = <&cpg CPG_MOD 912>;
226 resets = <&cpg 912>;
239 clocks = <&cpg CPG_MOD 911>;
[all …]
H A Dr8a774b1.dtsi10 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
84 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
95 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
162 clocks = <&cpg CPG_MOD 402>;
164 resets = <&cpg 402>;
178 clocks = <&cpg CPG_MOD 912>;
180 resets = <&cpg 912>;
193 clocks = <&cpg CPG_MOD 911>;
195 resets = <&cpg 911>;
208 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77951.dtsi8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
152 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
166 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
180 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
194 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
210 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
223 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
236 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
249 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
362 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr8a77980.dtsi9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
35 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
55 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
65 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
136 clocks = <&cpg CPG_MOD 402>;
138 resets = <&cpg 402>;
146 clocks = <&cpg CPG_CORE R8A77980_CLK_OSC>;
161 clocks = <&cpg CPG_MOD 912>;
163 resets = <&cpg 912>;
[all …]
H A Dr8a77970.dtsi9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
35 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
107 clocks = <&cpg CPG_MOD 402>;
109 resets = <&cpg 402>;
117 clocks = <&cpg CPG_CORE R8A77970_CLK_OSC>;
119 resets = <&cpg 401>;
133 clocks = <&cpg CPG_MOD 912>;
135 resets = <&cpg 912>;
148 clocks = <&cpg CPG_MOD 911>;
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
99 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
167 clocks = <&cpg CPG_MOD 402>;
169 resets = <&cpg 402>;
183 clocks = <&cpg CPG_MOD 912>;
185 resets = <&cpg 912>;
198 clocks = <&cpg CPG_MOD 911>;
200 resets = <&cpg 911>;
213 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
35 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
46 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
95 clocks = <&cpg CPG_MOD 402>;
97 resets = <&cpg 402>;
111 clocks = <&cpg CPG_MOD 912>;
113 resets = <&cpg 912>;
126 clocks = <&cpg CPG_MOD 911>;
128 resets = <&cpg 911>;
141 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
55 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
66 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
124 clocks = <&cpg CPG_MOD 402>;
126 resets = <&cpg 402>;
140 clocks = <&cpg CPG_MOD 912>;
142 resets = <&cpg 912>;
155 clocks = <&cpg CPG_MOD 911>;
157 resets = <&cpg 911>;
170 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7745.dtsi10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
74 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
85 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
139 clocks = <&cpg CPG_MOD 912>;
141 resets = <&cpg 912>;
154 clocks = <&cpg CPG_MOD 911>;
156 resets = <&cpg 911>;
169 clocks = <&cpg CPG_MOD 910>;
171 resets = <&cpg 910>;
184 clocks = <&cpg CPG_MOD 909>;
[all …]
H A Dr8a7742.dtsi8 #include <dt-bindings/clock/r8a7742-cpg-mssr.h>
57 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
79 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
101 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
123 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
145 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
155 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
165 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
175 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
248 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr8a7743.dtsi10 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
59 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
79 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
144 clocks = <&cpg CPG_MOD 402>;
146 resets = <&cpg 402>;
160 clocks = <&cpg CPG_MOD 912>;
162 resets = <&cpg 912>;
175 clocks = <&cpg CPG_MOD 911>;
177 resets = <&cpg 911>;
190 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7744.dtsi10 #include <dt-bindings/clock/r8a7744-cpg-mssr.h>
59 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
79 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
144 clocks = <&cpg CPG_MOD 402>;
146 resets = <&cpg 402>;
160 clocks = <&cpg CPG_MOD 912>;
162 resets = <&cpg 912>;
175 clocks = <&cpg CPG_MOD 911>;
177 resets = <&cpg 911>;
190 clocks = <&cpg CPG_MOD 910>;
[all …]

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