Home
last modified time | relevance | path

Searched refs:cmn_pll (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/clk/qcom/
H A Dipq-cmn-pll.c187 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); in clk_cmn_pll_recalc_rate() local
194 regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); in clk_cmn_pll_recalc_rate()
218 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); in clk_cmn_pll_set_rate() local
230 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, in clk_cmn_pll_set_rate()
241 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, in clk_cmn_pll_set_rate()
247 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION, in clk_cmn_pll_set_rate()
255 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL, in clk_cmn_pll_set_rate()
264 ret = regmap_clear_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, in clk_cmn_pll_set_rate()
270 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, in clk_cmn_pll_set_rate()
276 return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val, in clk_cmn_pll_set_rate()
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dipq5424.dtsi285 cmn_pll: clock-controller@9b000 { label
293 assigned-clocks = <&cmn_pll IPQ5424_CMN_PLL_CLK>;
826 clocks = <&cmn_pll IPQ5424_XO_24MHZ_CLK>,
827 <&cmn_pll IPQ5424_NSS_300MHZ_CLK>,
828 <&cmn_pll IPQ5424_PPE_375MHZ_CLK>,
H A Dipq9574.dtsi351 cmn_pll: clock-controller@9b000 { label
359 assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
1259 <&cmn_pll NSS_1200MHZ_CLK>,
1260 <&cmn_pll PPE_353MHZ_CLK>,
H A Dipq5018.dtsi248 cmn_pll: clock-controller@9b000 { label
258 assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;