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Searched refs:amdgpu_ring_write (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/ !
H A Djpeg_v1_0.c186 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_insert_start()
188 amdgpu_ring_write(ring, 0x68e04); in jpeg_v1_0_decode_ring_insert_start()
190 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_start()
191 amdgpu_ring_write(ring, 0x80010000); in jpeg_v1_0_decode_ring_insert_start()
205 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_insert_end()
207 amdgpu_ring_write(ring, 0x68e04); in jpeg_v1_0_decode_ring_insert_end()
209 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_end()
210 amdgpu_ring_write(ring, 0x00010000); in jpeg_v1_0_decode_ring_insert_end()
230 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_emit_fence()
232 amdgpu_ring_write(ring, seq); in jpeg_v1_0_decode_ring_emit_fence()
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H A Dvcn_sw_ring.c32 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); in vcn_dec_sw_ring_emit_fence()
33 amdgpu_ring_write(ring, addr); in vcn_dec_sw_ring_emit_fence()
34 amdgpu_ring_write(ring, upper_32_bits(addr)); in vcn_dec_sw_ring_emit_fence()
35 amdgpu_ring_write(ring, seq); in vcn_dec_sw_ring_emit_fence()
36 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); in vcn_dec_sw_ring_emit_fence()
41 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); in vcn_dec_sw_ring_insert_end()
49 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); in vcn_dec_sw_ring_emit_ib()
50 amdgpu_ring_write(ring, vmid); in vcn_dec_sw_ring_emit_ib()
51 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_dec_sw_ring_emit_ib()
52 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_dec_sw_ring_emit_ib()
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H A Dsdma_v2_4.c231 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v2_4_ring_insert_nop()
234 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v2_4_ring_insert_nop()
257 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v2_4_ring_emit_ib()
260 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
261 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
262 amdgpu_ring_write(ring, ib->length_dw); in sdma_v2_4_ring_emit_ib()
263 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
264 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
284 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v2_4_ring_emit_hdp_flush()
287 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v2_4_ring_emit_hdp_flush()
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H A Dcik_sdma.c206 amdgpu_ring_write(ring, ring->funcs->nop | in cik_sdma_ring_insert_nop()
209 amdgpu_ring_write(ring, ring->funcs->nop); in cik_sdma_ring_insert_nop()
233 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); in cik_sdma_ring_emit_ib()
234 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_emit_ib()
235 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
236 amdgpu_ring_write(ring, ib->length_dw); in cik_sdma_ring_emit_ib()
258 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_sdma_ring_emit_hdp_flush()
259 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in cik_sdma_ring_emit_hdp_flush()
260 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); in cik_sdma_ring_emit_hdp_flush()
261 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
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H A Dsdma_v6_0.c150 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v6_0_ring_init_cond_exec()
151 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
152 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
153 amdgpu_ring_write(ring, 1); in sdma_v6_0_ring_init_cond_exec()
157 amdgpu_ring_write(ring, 0); in sdma_v6_0_ring_init_cond_exec()
249 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v6_0_ring_insert_nop()
252 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v6_0_ring_insert_nop()
283 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v6_0_ring_emit_ib()
286 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v6_0_ring_emit_ib()
287 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v6_0_ring_emit_ib()
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H A Dsdma_v3_0.c407 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v3_0_ring_insert_nop()
410 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v3_0_ring_insert_nop()
433 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v3_0_ring_emit_ib()
436 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
437 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
438 amdgpu_ring_write(ring, ib->length_dw); in sdma_v3_0_ring_emit_ib()
439 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
440 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
460 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v3_0_ring_emit_hdp_flush()
463 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v3_0_ring_emit_hdp_flush()
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H A Dsdma_v5_2.c148 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_2_ring_init_cond_exec()
149 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_init_cond_exec()
150 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_init_cond_exec()
151 amdgpu_ring_write(ring, 1); in sdma_v5_2_ring_init_cond_exec()
155 amdgpu_ring_write(ring, 0); in sdma_v5_2_ring_init_cond_exec()
262 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_2_ring_insert_nop()
265 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_2_ring_insert_nop()
296 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v5_2_ring_emit_ib()
299 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_2_ring_emit_ib()
300 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_2_ring_emit_ib()
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H A Dsdma_v5_0.c308 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_0_ring_init_cond_exec()
309 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_init_cond_exec()
310 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_init_cond_exec()
311 amdgpu_ring_write(ring, 1); in sdma_v5_0_ring_init_cond_exec()
315 amdgpu_ring_write(ring, 0); in sdma_v5_0_ring_init_cond_exec()
414 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_0_ring_insert_nop()
417 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_0_ring_insert_nop()
448 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v5_0_ring_emit_ib()
451 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
452 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_0_ring_emit_ib()
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H A Dgfx_v11_0.c359 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx11_kiq_set_resources()
360 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx11_kiq_set_resources()
363 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx11_kiq_set_resources()
364 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx11_kiq_set_resources()
365 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ in gfx11_kiq_set_resources()
366 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ in gfx11_kiq_set_resources()
367 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx11_kiq_set_resources()
368 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx11_kiq_set_resources()
395 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx11_kiq_map_queues()
397 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_map_queues()
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H A Dgfx_v12_0.c295 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v12_0_kiq_set_resources()
296 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx_v12_0_kiq_set_resources()
298 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v12_0_kiq_set_resources()
299 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v12_0_kiq_set_resources()
300 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v12_0_kiq_set_resources()
301 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v12_0_kiq_set_resources()
302 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v12_0_kiq_set_resources()
303 amdgpu_ring_write(kiq_ring, 0); in gfx_v12_0_kiq_set_resources()
330 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v12_0_kiq_map_queues()
332 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx_v12_0_kiq_map_queues()
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H A Dsdma_v4_4_2.c358 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v4_4_2_ring_insert_nop()
361 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v4_4_2_ring_insert_nop()
384 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v4_4_2_ring_emit_ib()
387 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_4_2_ring_emit_ib()
388 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v4_4_2_ring_emit_ib()
389 amdgpu_ring_write(ring, ib->length_dw); in sdma_v4_4_2_ring_emit_ib()
390 amdgpu_ring_write(ring, 0); in sdma_v4_4_2_ring_emit_ib()
391 amdgpu_ring_write(ring, 0); in sdma_v4_4_2_ring_emit_ib()
401 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v4_4_2_wait_reg_mem()
407 amdgpu_ring_write(ring, addr0); in sdma_v4_4_2_wait_reg_mem()
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H A Dsdma_v4_0.c791 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v4_0_ring_insert_nop()
794 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v4_0_ring_insert_nop()
817 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v4_0_ring_emit_ib()
820 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_0_ring_emit_ib()
821 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v4_0_ring_emit_ib()
822 amdgpu_ring_write(ring, ib->length_dw); in sdma_v4_0_ring_emit_ib()
823 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
824 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
834 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v4_0_wait_reg_mem()
840 amdgpu_ring_write(ring, addr0); in sdma_v4_0_wait_reg_mem()
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H A Dgfx_v10_0.c3715 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx10_kiq_set_resources()
3716 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx10_kiq_set_resources()
3718 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx10_kiq_set_resources()
3719 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx10_kiq_set_resources()
3720 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ in gfx10_kiq_set_resources()
3721 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ in gfx10_kiq_set_resources()
3722 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx10_kiq_set_resources()
3723 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx10_kiq_set_resources()
3747 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx10_kiq_map_queues()
3749 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx10_kiq_map_queues()
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H A Damdgpu_vce.c1115 amdgpu_ring_write(ring, VCE_CMD_IB); in amdgpu_vce_ring_emit_ib()
1116 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1117 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1118 amdgpu_ring_write(ring, ib->length_dw); in amdgpu_vce_ring_emit_ib()
1135 amdgpu_ring_write(ring, VCE_CMD_FENCE); in amdgpu_vce_ring_emit_fence()
1136 amdgpu_ring_write(ring, addr); in amdgpu_vce_ring_emit_fence()
1137 amdgpu_ring_write(ring, upper_32_bits(addr)); in amdgpu_vce_ring_emit_fence()
1138 amdgpu_ring_write(ring, seq); in amdgpu_vce_ring_emit_fence()
1139 amdgpu_ring_write(ring, VCE_CMD_TRAP); in amdgpu_vce_ring_emit_fence()
1140 amdgpu_ring_write(ring, VCE_CMD_END); in amdgpu_vce_ring_emit_fence()
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H A Djpeg_v2_5.c494 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_6_dec_ring_insert_start()
496 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ in jpeg_v2_6_dec_ring_insert_start()
498 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_6_dec_ring_insert_start()
500 amdgpu_ring_write(ring, 0x80000000 | (1 << (ring->me * 2 + 14))); in jpeg_v2_6_dec_ring_insert_start()
512 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_6_dec_ring_insert_end()
514 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ in jpeg_v2_6_dec_ring_insert_end()
516 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_6_dec_ring_insert_end()
518 amdgpu_ring_write(ring, (1 << (ring->me * 2 + 14))); in jpeg_v2_6_dec_ring_insert_end()
H A Damdgpu_amdkfd_gfx_v10_3.c302 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in hiq_mqd_load_v10_3()
303 amdgpu_ring_write(kiq_ring, in hiq_mqd_load_v10_3()
313 amdgpu_ring_write(kiq_ring, in hiq_mqd_load_v10_3()
315 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in hiq_mqd_load_v10_3()
316 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in hiq_mqd_load_v10_3()
317 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in hiq_mqd_load_v10_3()
318 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in hiq_mqd_load_v10_3()
H A Damdgpu_amdkfd_gfx_v11.c287 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in hiq_mqd_load_v11()
288 amdgpu_ring_write(kiq_ring, in hiq_mqd_load_v11()
298 amdgpu_ring_write(kiq_ring, in hiq_mqd_load_v11()
300 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in hiq_mqd_load_v11()
301 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in hiq_mqd_load_v11()
302 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in hiq_mqd_load_v11()
303 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in hiq_mqd_load_v11()
H A Damdgpu_amdkfd_gfx_v10.c316 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_hiq_mqd_load()
317 amdgpu_ring_write(kiq_ring, in kgd_hiq_mqd_load()
327 amdgpu_ring_write(kiq_ring, in kgd_hiq_mqd_load()
329 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in kgd_hiq_mqd_load()
330 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in kgd_hiq_mqd_load()
331 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in kgd_hiq_mqd_load()
332 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in kgd_hiq_mqd_load()
H A Damdgpu_amdkfd_gfx_v9.c327 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_gfx_v9_hiq_mqd_load()
328 amdgpu_ring_write(kiq_ring, in kgd_gfx_v9_hiq_mqd_load()
338 amdgpu_ring_write(kiq_ring, in kgd_gfx_v9_hiq_mqd_load()
340 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in kgd_gfx_v9_hiq_mqd_load()
341 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in kgd_gfx_v9_hiq_mqd_load()
342 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in kgd_gfx_v9_hiq_mqd_load()
343 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in kgd_gfx_v9_hiq_mqd_load()
H A Damdgpu_jpeg.c171 amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0)); in amdgpu_jpeg_dec_ring_test_ring()
172 amdgpu_ring_write(ring, 0xABADCAFE); in amdgpu_jpeg_dec_ring_test_ring()
H A Damdgpu_ring.h493 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) in amdgpu_ring_write() function
H A Damdgpu_ring.c893 amdgpu_ring_write(ring, ring->ring_backup[i]); in amdgpu_ring_reset_helper_end()