Searched refs:allow_rcg (Results 1 – 1 of 1) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| H A D | dcn35_dccg.c | 138 static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg) in dccg35_set_dsc_clk_rcg() argument
142 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg) in dccg35_set_dsc_clk_rcg()
147 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dsc_clk_rcg()
150 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dsc_clk_rcg()
153 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dsc_clk_rcg()
156 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dsc_clk_rcg()
164 if (!allow_rcg) in dccg35_set_dsc_clk_rcg()
394 static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg) in dccg35_set_dppclk_rcg() argument
398 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg) in dccg35_set_dppclk_rcg()
403 REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); in dccg35_set_dppclk_rcg()
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