Searched refs:aenq (Results 1 – 9 of 9) sorted by relevance
204 struct efa_com_aenq *aenq = &edev->aenq; in efa_com_admin_init_aenq() local214 size = EFA_ASYNC_QUEUE_DEPTH * sizeof(*aenq->entries); in efa_com_admin_init_aenq()215 aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr, in efa_com_admin_init_aenq()217 if (!aenq->entries) in efa_com_admin_init_aenq()220 aenq->aenq_handlers = aenq_handlers; in efa_com_admin_init_aenq()221 aenq->depth = EFA_ASYNC_QUEUE_DEPTH; in efa_com_admin_init_aenq()222 aenq->cc = 0; in efa_com_admin_init_aenq()223 aenq->phase = 1; in efa_com_admin_init_aenq()225 addr_low = lower_32_bits(aenq->dma_addr); in efa_com_admin_init_aenq()226 addr_high = upper_32_bits(aenq->dma_addr); in efa_com_admin_init_aenq()[all …]
637 get_resp.u.aenq.supported_groups, in efa_com_set_aenq_config()638 get_resp.u.aenq.enabled_groups); in efa_com_set_aenq_config()640 if ((get_resp.u.aenq.supported_groups & groups) != groups) { in efa_com_set_aenq_config()644 groups, get_resp.u.aenq.supported_groups); in efa_com_set_aenq_config()648 cmd.u.aenq.enabled_groups = groups; in efa_com_set_aenq_config()
871 struct efa_admin_feature_aenq_desc aenq; member894 struct efa_admin_feature_aenq_desc aenq; member
108 struct efa_com_aenq aenq; member
612 edev->aenq.msix_vector_idx = dev->admin_msix_vector_idx; in efa_probe_device()
137 struct ena_com_aenq *aenq = &ena_dev->aenq; in ena_com_admin_init_aenq() local141 ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; in ena_com_admin_init_aenq()143 aenq->entries = dma_alloc_coherent(ena_dev->dmadev, size, &aenq->dma_addr, GFP_KERNEL); in ena_com_admin_init_aenq()145 if (!aenq->entries) { in ena_com_admin_init_aenq()150 aenq->head = aenq->q_depth; in ena_com_admin_init_aenq()151 aenq->phase = 1; in ena_com_admin_init_aenq()153 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); in ena_com_admin_init_aenq()154 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); in ena_com_admin_init_aenq()160 aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; in ena_com_admin_init_aenq()171 aenq->aenq_handlers = aenq_handlers; in ena_com_admin_init_aenq()[all …]
353 struct ena_com_aenq aenq; member397 struct ena_admin_feature_aenq_desc aenq; member
1088 struct ena_admin_feature_aenq_desc aenq; member1125 struct ena_admin_feature_aenq_desc aenq; member
3175 aenq_groups &= get_feat_ctx->aenq.supported_groups; in ena_device_init()