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Searched refs:_parents (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mux.h47 #define __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \ argument
61 .parent_names = _parents, \
68 #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
71 __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
72 NULL, ARRAY_SIZE(_parents), _mux_ofs, \
76 #define GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, _paridx, \ argument
79 __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
89 #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
92 GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
97 #define MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \ argument
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H A Dclk-mtk.h114 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
124 .parent_names = _parents, \
125 .num_parents = ARRAY_SIZE(_parents), \
134 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
136 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
143 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
144 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
147 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
148 MUX_FLAGS(_id, _name, _parents, _reg, \
151 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
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H A Dclk-mt6795-topckgen.c21 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
22 MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \
26 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
27 TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
H A Dclk-mt8173-topckgen.c22 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
23 MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \
27 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
28 TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
/linux/drivers/clk/sunxi-ng/
H A Dccu_mp.h34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
49 _parents, \
55 #define SUNXI_CCU_MP_DATA_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, \ argument
71 _parents, \
77 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
90 _parents, \
96 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
101 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
107 #define SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(_struct, _name, _parents, _reg, \ argument
124 _parents, \
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H A Dccu_div.h128 _parents, _table, \ argument
140 _parents, \
147 _parents, _table, \ argument
159 _parents, \
166 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
170 _parents, NULL, \
175 #define SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(_struct, _name, _parents, \ argument
180 _parents, NULL, \
185 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
189 _parents, NULL, \
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H A Dccu_nkm.h36 #define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \ argument
52 _parents, \
/linux/drivers/clk/sprd/
H A Dmux.h39 #define SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \ argument
46 .hw.init = _fn(_name, _parents, \
51 #define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table, \ argument
53 SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument
59 SPRD_MUX_CLK_TABLE(_struct, _name, _parents, NULL, \
62 #define SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, _table, \ argument
64 SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument
70 SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, NULL, \
/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
134 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
136 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
141 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
143 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
146 #define MUX8(_name, _parents, _offset, \ argument
148 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
150 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
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H A Dclk-tegra124.c97 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
98 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
101 _parents##_idx, 0, _lock)
103 #define NODIV(_name, _parents, _offset, \ argument
106 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
109 _clk_id, _parents##_idx, 0, _lock)
/linux/drivers/clk/pxa/
H A Dclk-pxa.h18 static const char *const name ## _parents[] __initconst
32 name ## _parents, \
33 ARRAY_SIZE(name ## _parents), \
47 name ## _parents, \
48 ARRAY_SIZE(name ## _parents), \
64 name ## _parents, \
65 ARRAY_SIZE(name ## _parents), \
81 name ## _parents, \
82 ARRAY_SIZE(name ## _parents), \
/linux/drivers/clk/actions/
H A Dowl-mux.h34 #define OWL_MUX(_struct, _name, _parents, _reg, \ argument
41 _parents, \
/linux/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c101 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ argument
107 .parents = _parents, \
187 #define CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(_name, _parents, _ops, _flags) \ argument
191 .parent_data = _parents, \
/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-common.h20 #define CV1800_CLK_COMMON(_name, _parents, _op, _flags) \ argument
22 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parents, \
H A Dclk-sg2044-pll.c385 #define SG2044_CLK_COMMON_PDATA(_id, _name, _parents, _op, _flags) \ argument
387 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parents, \
H A Dclk-sg2044.c288 #define SG2044_CLK_COMMON_PDATA(_id, _name, _parents, _op, _flags) \ argument
290 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parents, \
295 #define SG2044_CLK_COMMON_PHWS(_id, _name, _parents, _op, _flags) \ argument
297 .hw.init = CLK_HW_INIT_PARENTS_HW(_name, _parents, \
/linux/include/linux/
H A Dclk-provider.h1538 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
1542 .parent_names = _parents, \
1543 .num_parents = ARRAY_SIZE(_parents), \
1547 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ argument
1551 .parent_hws = _parents, \
1552 .num_parents = ARRAY_SIZE(_parents), \
1556 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ argument
1560 .parent_data = _parents, \
1561 .num_parents = ARRAY_SIZE(_parents), \
H A Dsh_clk.h175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
182 .parent_table = _parents, \
/linux/drivers/clk/
H A Dclk-stm32h7.c567 #define M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, _flags)\ argument
570 .parents = _parents,\
571 .num_parents = ARRAY_SIZE(_parents),\
578 #define M_MCLOC(_name, _parents, _mux_offset, _mux_shift, _mux_width)\ argument
579 M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, 0)\
1177 #define M_MCO_F(_name, _parents, _mux_offset, _mux_shift, _mux_width,\ argument
1185 .parent_name = _parents,\
1186 .num_parents = ARRAY_SIZE(_parents),\
H A Dclk-bm1880.c160 #define GATE_MUX(_id, _name, _parents, _gate_reg, _gate_shift, \ argument
163 .parents = _parents, \
164 .num_parents = ARRAY_SIZE(_parents), \
/linux/drivers/clk/stm32/
H A Dclk-stm32mp1.c1221 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument
1225 .parent_names = _parents,\
1226 .num_parents = ARRAY_SIZE(_parents),\
1237 #define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\ argument
1241 .parent_names = _parents,\
1242 .num_parents = ARRAY_SIZE(_parents),\
1371 #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\ argument
1375 .parent_names = _parents,\
1376 .num_parents = ARRAY_SIZE(_parents),\
1392 #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\ argument
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/linux/drivers/clk/meson/
H A Daxg-audio.c376 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \ argument
377 AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents, \