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Searched refs:_MMIO (Results 1 – 25 of 56) sorted by relevance

123

/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_regs.h22 #define PERF_REG(offset) _MMIO(offset)
25 #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
32 #define RPM_CONFIG0 _MMIO(0xd00)
43 #define RPM_CONFIG1 _MMIO(0xd04)
47 #define RCP_CONFIG _MMIO(0xd08)
49 #define RC6_LOCATION _MMIO(0xd40)
51 #define RC6_CTX_BASE _MMIO(0xd48)
54 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4)
55 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4)
56 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
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H A Dintel_engine_regs.h11 #define RING_EXCC(base) _MMIO((base) + 0x28)
12 #define RING_TAIL(base) _MMIO((base) + 0x30)
14 #define RING_HEAD(base) _MMIO((base) + 0x34)
19 #define RING_START(base) _MMIO((base) + 0x38)
20 #define RING_CTL(base) _MMIO((base) + 0x3c)
32 #define RING_SYNC_0(base) _MMIO((base) + 0x40)
33 #define RING_SYNC_1(base) _MMIO((base) + 0x44)
34 #define RING_SYNC_2(base) _MMIO((base) + 0x48)
47 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
55 #define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
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/linux/drivers/gpu/drm/i915/
H A Di915_reg.h119 #define GU_CNTL_PROTECTED _MMIO(0x10100C)
122 #define GU_CNTL _MMIO(0x101010)
125 #define GU_DEBUG _MMIO(0x101018)
128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
150 #define DEBUG_RESET_I830 _MMIO(0x6070)
158 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
180 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
181 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
196 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
209 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
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H A Di915_perf_oa_regs.h11 #define GEN7_OACONTROL _MMIO(0x2360)
28 #define GEN8_OACTXID _MMIO(0x2364)
30 #define GEN8_OA_DEBUG _MMIO(0x2B04)
36 #define GEN8_OACONTROL _MMIO(0x2B00)
45 #define GEN8_OACTXCONTROL _MMIO(0x2360)
51 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
57 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
58 #define GEN8_OABUFFER _MMIO(0x2b14)
61 #define GEN7_OASTATUS1 _MMIO(0x2364)
67 #define GEN7_OASTATUS2 _MMIO(0x2368)
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/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_reg.h16 #define GUC_STATUS _MMIO(0xc000)
33 #define GUC_HEADER_INFO _MMIO(0xc014)
35 #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
38 #define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4)
39 #define MEDIA_SOFT_SCRATCH(n) _MMIO(0x190310 + (n) * 4)
42 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
45 #define DMA_ADDR_0_LOW _MMIO(0xc300)
46 #define DMA_ADDR_0_HIGH _MMIO(0xc304)
47 #define DMA_ADDR_1_LOW _MMIO(0xc308)
48 #define DMA_ADDR_1_HIGH _MMIO(0xc30c)
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_tv_regs.h12 #define TV_CTL _MMIO(0x68000)
82 #define TV_DAC _MMIO(0x68004)
133 #define TV_CSC_Y _MMIO(0x68010)
139 #define TV_CSC_Y2 _MMIO(0x68014)
150 #define TV_CSC_U _MMIO(0x68018)
156 #define TV_CSC_U2 _MMIO(0x6801c)
167 #define TV_CSC_V _MMIO(0x68020)
173 #define TV_CSC_V2 _MMIO(0x68024)
184 #define TV_CLR_KNOBS _MMIO(0x68028)
198 #define TV_CLR_LEVEL _MMIO(0x6802c)
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H A Dintel_combo_phy_regs.h27 #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
31 #define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
46 #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
54 #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
57 #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
59 #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
69 #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
72 #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
74 #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
86 #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
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H A Di9xx_wm_regs.h9 #define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
24 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
37 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
44 #define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
55 #define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
71 #define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
82 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
89 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
98 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
101 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
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H A Dintel_vdsc_regs.h12 #define DSS_CTL1 _MMIO(0x67400)
23 #define DSS_CTL2 _MMIO(0x67404)
54 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
55 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
58 #define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)
59 #define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)
81 #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
82 #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
83 #define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4))
212 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
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H A Dintel_dsb_regs.h15 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
16 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
17 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
25 #define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc)
31 #define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10)
37 #define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14)
38 #define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)
39 #define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24)
53 #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
66 #define DSB_CURRENT_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x2c)
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H A Dintel_audio_regs.h11 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
16 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
29 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
39 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
47 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
112 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
113 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
124 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
127 #define AUD_FREQ_CNTRL _MMIO(0x65900)
128 #define AUD_PIN_BUF_CTL _MMIO(0x48414)
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H A Dskl_watermark_regs.h31 #define MBUS_UBOX_CTL _MMIO(0x4503C)
32 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
33 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
35 #define MBUS_CTL _MMIO(0x4438C)
60 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
74 #define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)
75 #define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)
76 #define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)
80 #define MTL_LATENCY_SAGV _MMIO(0x4578c)
83 #define LNL_PKG_C_LATENCY _MMIO(0x46460)
H A Dintel_backlight_regs.h24 #define BLC_PWM_CTL2 _MMIO(0x61250) /* 965+ only */
47 #define BLC_PWM_CTL _MMIO(0x61254)
69 #define BLC_HIST_CTL _MMIO(0x61260)
74 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
75 #define BLC_PWM_CPU_CTL _MMIO(0x48254)
77 #define HSW_BLC_PWM2_CTL _MMIO(0x48350)
81 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
85 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
106 #define UTIL_PIN_CTL _MMIO(0x48400)
H A Dintel_hdcp_regs.h14 #define HDCP_KEY_CONF _MMIO(0x66c00)
18 #define HDCP_KEY_STATUS _MMIO(0x66c04)
24 #define HDCP_AKSV_LO _MMIO(0x66c10)
25 #define HDCP_AKSV_HI _MMIO(0x66c14)
28 #define HDCP_REP_CTL _MMIO(0x66d00)
59 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
60 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
61 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
62 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
63 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
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H A Dintel_fdi_regs.h11 #define FDI_PLL_BIOS_0 _MMIO(0x46000)
13 #define FDI_PLL_BIOS_1 _MMIO(0x46004)
14 #define FDI_PLL_BIOS_2 _MMIO(0x46008)
15 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
16 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
17 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
19 #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
148 #define FDI_PLL_CTL_1 _MMIO(0xfe000)
149 #define FDI_PLL_CTL_2 _MMIO(0xfe004)
H A Dintel_gmbus_regs.h13 #define GPIO(__display, gpio) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5010 + 4 * (gpio))
30 #define GMBUS0(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5100)
40 #define GMBUS1(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5104)
57 #define GMBUS2(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5108)
67 #define GMBUS3(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x510c)
70 #define GMBUS4(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5110)
78 #define GMBUS5(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5120)
H A Dintel_dp_aux_regs.h28 #define VLV_DP_AUX_CH_CTL(aux_ch) _MMIO(VLV_DISPLAY_BASE + \
38 _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
80 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, \
82 #define VLV_DP_AUX_CH_DATA(aux_ch, i) _MMIO(VLV_DISPLAY_BASE + _PORT(aux_ch, _DPA_AUX_CH_DATA1, \
87 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_…
92 _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
102 #define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04)
H A Dvlv_dsi_pll_regs.h11 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
13 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
18 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
81 #define BXT_DSI_PLL_CTL _MMIO(0x161000)
105 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
H A Dintel_crt_regs.h11 #define ADPA _MMIO(0x61100)
12 #define PCH_ADPA _MMIO(0xe1100)
13 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
48 #define _VGA_MSR_WRITE _MMIO(0x3c2)
H A Dintel_cmtg_regs.h11 #define CMTG_CLK_SEL _MMIO(0x46160)
17 #define TRANS_CMTG_CTL_A _MMIO(0x6fa88)
18 #define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
H A Dintel_color_regs.h33 #define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
48 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
65 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
69 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1…
222 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * …
223 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX…
224 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_…
308 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + …
309 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * …
H A Dintel_vga_regs.h11 #define VGACNTRL _MMIO(0x71400)
12 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
13 #define CPU_VGACNTRL _MMIO(0x41000)
/linux/drivers/gpu/drm/i915/gvt/
H A Dreg.h68 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
69 (_MMIO(0x50090))) : \
70 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
71 (_MMIO(0x50098))) : \
72 (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
73 (_MMIO(0x5009C))) : \
74 (_MMIO(0x50080))))); })
114 #define PCH_GPIO_BASE _MMIO(0xc5010)
116 #define PCH_GMBUS0 _MMIO(0xc5100)
117 #define PCH_GMBUS1 _MMIO(0xc5104)
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H A Dhandlers.c76 #define PCH_PP_STATUS _MMIO(0xc7200)
77 #define PCH_PP_CONTROL _MMIO(0xc7204)
78 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
79 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
80 #define PCH_PP_DIVISOR _MMIO(0xc7210)
739 _MMIO(0xd80),
746 _MMIO(0x2690),
747 _MMIO(0x2694),
748 _MMIO(0x2698),
749 _MMIO(0x2754),
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/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_regs.h16 #define KCR_INIT(base) _MMIO((base) + 0xf0)
22 #define KCR_SIP(base) _MMIO((base) + 0x260)
25 #define KCR_GLOBAL_TERMINATE(base) _MMIO((base) + 0xf8)

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