Home
last modified time | relevance | path

Searched refs:_MASKED_BIT_ENABLE (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/i915/gvt/
H A Dreg.h94 (((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
H A Dmmio_context.c478 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); in is_inhibit_context()
H A Dhandlers.c2050 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); in ring_mode_mmio_write()
2053 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); in ring_mode_mmio_write()
2155 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); in csfe_chicken1_mmio_write()
2537 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
/linux/drivers/gpu/drm/xe/
H A Dxe_execlist.c50 u32 ring_mode = _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE); in __start_lrc()
64 _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE)); in __start_lrc()
86 ring_mode |= _MASKED_BIT_ENABLE(GFX_MSIX_INTERRUPT_ENABLE); in __start_lrc()
H A Dxe_hw_engine.c330 u32 ring_mode = _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE); in xe_hw_engine_enable_ring()
334 _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE)); in xe_hw_engine_enable_ring()
341 ring_mode |= _MASKED_BIT_ENABLE(GFX_MSIX_INTERRUPT_ENABLE); in xe_hw_engine_enable_ring()
H A Dxe_lrc.c640 regs[CTX_CONTEXT_CONTROL] = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | in set_context_control()
645 _MASKED_BIT_ENABLE(CTX_CTRL_INDIRECT_RING_STATE_ENABLE); in set_context_control()
1207 *cmd++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE); in setup_invalidate_state_cache_wa()
1545 _MASKED_BIT_ENABLE(CTX_CTRL_RUN_ALONE)); in xe_lrc_init()
1550 _MASKED_BIT_ENABLE(CTX_CTRL_PXP_ENABLE)); in xe_lrc_init()
H A Dxe_eu_stall.c447 write_ptr_reg = _MASKED_BIT_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP); in clear_dropped_eviction_line_bit()
677 _MASKED_BIT_ENABLE(DISABLE_DOP_GATING)); in xe_eu_stall_stream_enable()
H A Dxe_pxp.c315 u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) : in kcr_pxp_set_status()
H A Dxe_oa.c1085 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); in xe_oa_enable_metric_set()
1087 _MASKED_BIT_ENABLE(DISABLE_DOP_GATING)); in xe_oa_enable_metric_set()
1102 _MASKED_BIT_ENABLE(oa_debug) | in xe_oa_enable_metric_set()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_rc6.c379 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in chv_rc6_enable()
404 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in vlv_rc6_enable()
764 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); in vlv_residency_raw()
774 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); in vlv_residency_raw()
H A Dintel_ggtt_fencing.c918 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in intel_gt_init_swizzling()
922 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in intel_gt_init_swizzling()
926 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); in intel_gt_init_swizzling()
H A Dintel_ring_submission.c129 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | in flush_cs_tlb()
173 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in set_pp_dir()
720 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); in load_pd_dir()
769 *cs++ = _MASKED_BIT_ENABLE( in mi_set_context()
1056 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); in gen6_bsd_submit_request()
H A Dintel_workarounds.c301 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_masked_en()
307 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_mcr_masked_en()
667 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), in icl_ctx_workarounds_init()
1132 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), in hsw_gt_workarounds_init()
2273 _MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES), in rcs_engine_wa_init()
2664 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), in rcs_engine_wa_init()
2680 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), in rcs_engine_wa_init()
2880 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), in general_render_compute_wa_init()
H A Dintel_engine_cs.c1236 engine->tlb_inv.request = _MASKED_BIT_ENABLE(val); in intel_engine_init_tlb_invalidation()
1631 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); in __intel_engine_stop_cs()
1639 _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE)); in __intel_engine_stop_cs()
2555 _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); in xehp_enable_ccs_engines()
H A Dgen6_ppgtt.c70 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen6_ppgtt_enable()
H A Dintel_reset.c589 intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request)); in gen8_engine_reset_prepare()
H A Dintel_execlists_submission.c2937 mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE); in enable_execlists()
2939 mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE); in enable_execlists()
/linux/drivers/gpu/drm/i915/
H A Di915_reg_defs.h118 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) macro
H A Di915_perf.c2830 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | in gen8_enable_metric_set()
2873 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); in gen12_enable_metric_set()
2875 _MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING)); in gen12_enable_metric_set()
2880 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | in gen12_enable_metric_set()
4478 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); in mask_reg_value()
4486 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); in mask_reg_value()
H A Dintel_uncore.c135 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp.c69 u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) : in kcr_pxp_set_status()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_irq.c1622 _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); in i915gm_irq_cstate_wa_enable()
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_submission.c4417 _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); in start_engine()