Searched refs:WR_CONFIRM (Results 1 – 10 of 10) sorted by relevance
151 #define WR_CONFIRM (1 << 20) macro
275 #define WR_CONFIRM (1 << 20) macro
139 #define WR_CONFIRM (1 << 20) macro
387 #define WR_CONFIRM (1 << 20) macro
116 #define WR_CONFIRM (1 << 20) macro
520 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()636 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()6018 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()6027 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()6123 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v11_0_ring_emit_gfx_shadow()6235 WR_CONFIRM) | in gfx_v11_0_ring_emit_de_meta()6281 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()6287 cmd = WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()
525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v12_0_ring_test_ib()4528 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()4537 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()4656 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v12_0_ring_emit_wreg()4662 cmd = WR_CONFIRM; in gfx_v12_0_ring_emit_wreg()
4005 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()4098 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()8782 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8791 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8919 WR_CONFIRM) | in gfx_v10_0_ring_emit_ce_meta()8955 WR_CONFIRM) | in gfx_v10_0_ring_emit_de_meta()9001 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v10_0_ring_emit_wreg()9007 cmd = WR_CONFIRM; in gfx_v10_0_ring_emit_wreg()
1646 #define WR_CONFIRM (1 << 20) macro
1737 #define WR_CONFIRM (1 << 20) macro