Searched refs:SPU (Results 1 – 16 of 16) sorted by relevance
27 ate(2) to address a specific SPU context. When the context gets sched-28 uled to a physical SPU, it starts execution at the instruction pointer31 Execution of SPU code happens synchronously, meaning that spu_run does32 not return while the SPU is still running. If there is a need to exe-33 cute SPU code in parallel with other code on either the main CPU or37 When spu_run returns, the current value of the SPU instruction pointer63 on the SPU. The bit masks for the status codes are:66 SPU was stopped by stop-and-signal.69 SPU was stopped by halt.72 SPU is waiting for a channel.[all …]
10 spufs - the SPU file system16 The SPU file system is used on PowerPC machines that implement the Cell22 can use spu_create(2) to establish SPU contexts in the spufs root.24 Every SPU context is represented by a directory containing a predefined26 logical SPU. Users can change permissions on those files, but not actu-63 the contents of the local storage memory of the SPU. This can be65 data in the address space of the SPU. The possible operations on an71 file. The file size is the size of the local storage of the SPU,76 SPU local storage within the process address space. Only81 The first SPU to CPU communication mailbox. This file is read-only and[all …]
26 Processor Units (SPUs). It creates a new logical context for an SPU in28 point to a non-existing directory in the mount point of the SPU file36 descriptor is closed, the logical SPU context is destroyed.42 Allow mapping of some of the hardware registers of the SPU into67 EEXIST An SPU context already exists at the given path name.87 ENOSPC There are not enough SPU resources available to create a new88 context or the user specific limit for the number of SPU con-
4 SPU Filesystem
10 tristate "SPU file system"16 The SPU file system is used to access Synergistic Processing
895 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF, enumerator1012 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),1062 TMU1_TUNI2, SPU } },
7 * SPU - Seat Power Unit
780 Secure Processing Unit (SPU). The SPU driver registers skcipher,
81 3 processors on chip, Java ones, VPU, SPU, APU, maybe these are the124 - 0x9050: SPU control192 - Write 0x00000001 to register 0x9050 to stop the SPU.202 re-enable the SPU.
457 /* First part of the "SPU secure shared memory" region */463 /* Second part of the "SPU secure shared memory" region */
700 /* First part of the "SPU secure shared memory" region */706 /* Second part of the "SPU secure shared memory" region */
584 /* First part of the "SPU secure shared memory" region */590 /* Second part of the "SPU secure shared memory" region */
1771 /* First part of the "SPU secure shared memory" region */1777 /* Second part of the "SPU secure shared memory" region */
843 SPU
1926 D: Maintainer of SPU File System
24961 SPU FILE SYSTEM