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Searched refs:Register (Results 1 – 25 of 217) sorted by relevance

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/linux/drivers/gpu/drm/tyr/
H A Dregs.rs24 pub(crate) struct Register<const OFFSET: usize>; struct
26 impl<const OFFSET: usize> Register<OFFSET> { impl
40 pub(crate) const GPU_ID: Register<0x0> = Register;
41 pub(crate) const GPU_L2_FEATURES: Register<0x4> = Register;
42 pub(crate) const GPU_CORE_FEATURES: Register<0x8> = Register;
43 pub(crate) const GPU_CSF_ID: Register<0x1c> = Register;
44 pub(crate) const GPU_REVID: Register<0x280> = Register;
45 pub(crate) const GPU_TILER_FEATURES: Register<0xc> = Register;
46 pub(crate) const GPU_MEM_FEATURES: Register<0x10> = Register;
47 pub(crate) const GPU_MMU_FEATURES: Register<0x14> = Register;
[all …]
/linux/drivers/scsi/pcmcia/
H A Dnsp_io.h21 unsigned int Register,
24 unsigned int Register);
48 unsigned int Register) in nsp_index_read() argument
50 outb(Register, BaseAddr + INDEXREG); in nsp_index_read()
55 unsigned int Register, in nsp_index_write() argument
58 outb(Register, BaseAddr + INDEXREG); in nsp_index_write()
68 unsigned int Register, in nsp_multi_read_1() argument
72 insb(BaseAddr + Register, buf, count); in nsp_multi_read_1()
87 unsigned int Register, in nsp_multi_read_2() argument
91 insw(BaseAddr + Register, buf, count); in nsp_multi_read_2()
[all …]
/linux/Documentation/scsi/
H A Dhptiop.rst8 Controller Register Map
14 BAR0 offset Register
21 BAR2 offset Register
23 0x10 Inbound Message Register 0
24 0x14 Inbound Message Register 1
25 0x18 Outbound Message Register 0
26 0x1C Outbound Message Register 1
27 0x20 Inbound Doorbell Register
28 0x24 Inbound Interrupt Status Register
29 0x28 Inbound Interrupt Mask Register
[all …]
/linux/Documentation/driver-api/mmc/
H A Dmmc-dev-attrs.rst20 cid Card Identification Register
21 csd Card Specific Data Register
22 scr SD Card Configuration Register (SD only)
23 date Manufacturing Date (from CID Register)
24 fwrev Firmware/Product Revision (from CID Register)
26 hwrev Hardware/Product Revision (from CID Register)
28 manfid Manufacturer ID (from CID Register)
29 name Product Name (from CID Register)
30 oemid OEM/Application ID (from CID Register)
31 prv Product Revision (from CID Register)
[all …]
/linux/arch/arm/include/debug/
H A Dat91.S19 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
23 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
32 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
H A Dvf.S23 strb \rd, [\rx, #0x7] @ Data Register
27 1001: ldrb \rd, [\rx, #0x4] @ Status Register 1
H A Dstm32.S34 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
40 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
/linux/Documentation/devicetree/bindings/rtc/
H A Drtc-cmos.txt11 called "Register B".
13 called "Register A".
15 "Register A" and "B" are usually initialized by the firmware (BIOS for
/linux/Documentation/driver-api/cxl/platform/example-configurations/
H A Dhb-interleave.rst24 Register base : 0000010370400000
25 Register length : 0000000000010000
33 Register base : 0000010380800000
34 Register length : 0000000000010000
H A Done-dev-per-hb.rst25 Register base : 0000010370400000
26 Register length : 0000000000010000
34 Register base : 0000010380800000
35 Register length : 0000000000010000
H A Dflexible.rst29 Register base : 0000010370400000
30 Register length : 0000000000010000
38 Register base : 0000010380800000
39 Register length : 0000000000010000
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx27-pinctrl.txt24 Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
30 Register: DDIR
40 3 - Data Register
47 1 - Interrupt Status Register
/linux/Documentation/gpu/xe/
H A Dxe_gt_mcr.rst4 GT Multicast/Replicated (MCR) Register Support
8 :doc: GT Multicast/Replicated (MCR) Register Support
H A Dxe_rtp.rst4 Register Table Processing
8 :doc: Register Table Processing
/linux/Documentation/ABI/testing/
H A Ddebugfs-intel-iommu13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
191 IOMMU: dmar0 Register Base Address: 26be37000
200 IOMMU: dmar2 Register Base Address: fed91000
213 IOMMU: dmar0 Register Base Address: 26be37000
/linux/drivers/mtd/chips/
H A DKconfig167 erased. Each Protection Register can be accessed multiple times to
170 Each Protection Register has an associated Lock Register bit. When a
171 Lock Register bit is programmed, the associated Protection Register
173 because the Lock Register bits themselves are OTP, when programmed,
174 Lock Register bits cannot be erased. Therefore, when a Protection
175 Register is locked, it cannot be unlocked.
/linux/Documentation/arch/m68k/
H A Dbuddha-driver.rst10 Register map of the Buddha IDE controller and the
45 $7fe Speed-select Register: Read & Write
48 $800-$8ff IDE-Select 0 (Port 0, Register set 0)
50 $900-$9ff IDE-Select 1 (Port 0, Register set 1)
52 $a00-$aff IDE-Select 2 (Port 1, Register set 0)
54 $b00-$bff IDE-Select 3 (Port 1, Register set 1)
56 $c00-$cff IDE-Select 4 (Port 2, Register set 0,
59 $d00-$dff IDE-Select 5 (Port 3, Register set 1,
/linux/rust/kernel/net/phy/
H A Dreg.rs43 pub trait Register: private::Sealed { trait
104 impl Register for C22 {
196 impl Register for C45 {
/linux/drivers/crypto/caam/
H A DKconfig97 bool "Register algorithm implementations with the Crypto API"
128 bool "Register hash algorithm implementations with Crypto API"
137 bool "Register public key cryptography implementations with Crypto API"
146 bool "Register caam device for hwrng API"
155 bool "Register Pseudo random number generation implementation with Crypto API"
/linux/Documentation/arch/parisc/
H A Dregisters.rst2 Register Usage for Linux/PA-RISC
24 CR19 Interrupt Instruction Register
25 CR20 Interrupt Space Register
26 CR21 Interrupt Offset Register
108 Register usage notes, originally from John Marvin, with some additional
/linux/Documentation/arch/powerpc/
H A Dsyscall64-abi.rst47 Register preservation rules
49 Register preservation rules match the ELF ABI calling sequence with some
55 | Register | Preservation Rules | Purpose |
73 | Register | Preservation Rules | Purpose |
136 Register preservation rules
/linux/Documentation/arch/arm64/
H A Dcpu-feature-registers.rst116 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
149 2) ID_AA64PFR0_EL1 - Processor Feature Register 0
176 3) ID_AA64PFR1_EL1 - Processor Feature Register 1
191 4) MIDR_EL1 - Main ID Register
315 10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
323 11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
337 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
/linux/drivers/soc/rockchip/
H A DKconfig9 bool "Rockchip General Register Files support" if COMPILE_TEST
12 The General Register Files are a central component providing
/linux/Documentation/misc-devices/
H A Damd-sbi.rst28 Register sets is common across APML protocols. IOCTL is providing synchronization
44 * Register xfer
48 * APML Mailbox messages and Register xfer access are read-write,
/linux/arch/arm/include/asm/
H A Dvfpmacros.h36 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
61 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0

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