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Searched refs:RV_REG_SP (Results 1 – 3 of 3) sorted by relevance

/linux/arch/riscv/net/
H A Dbpf_jit_comp64.c236 emit_ld(RV_REG_RA, store_offset, RV_REG_SP, ctx); in __build_epilogue()
239 emit_ld(RV_REG_FP, store_offset, RV_REG_SP, ctx); in __build_epilogue()
242 emit_ld(RV_REG_S1, store_offset, RV_REG_SP, ctx); in __build_epilogue()
246 emit_ld(RV_REG_S2, store_offset, RV_REG_SP, ctx); in __build_epilogue()
250 emit_ld(RV_REG_S3, store_offset, RV_REG_SP, ctx); in __build_epilogue()
254 emit_ld(RV_REG_S4, store_offset, RV_REG_SP, ctx); in __build_epilogue()
258 emit_ld(RV_REG_S5, store_offset, RV_REG_SP, ctx); in __build_epilogue()
262 emit_ld(RV_REG_S6, store_offset, RV_REG_SP, ctx); in __build_epilogue()
266 emit_ld(RV_REG_ARENA, store_offset, RV_REG_SP, ctx); in __build_epilogue()
270 emit_addi(RV_REG_SP, RV_REG_SP, stack_adjust, ctx); in __build_epilogue()
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H A Dbpf_jit_comp32.c155 emit(rv_lw(RV_REG_RA, stack_adjust - 4, RV_REG_SP), ctx); in __build_epilogue()
156 emit(rv_lw(RV_REG_FP, stack_adjust - 8, RV_REG_SP), ctx); in __build_epilogue()
157 emit(rv_lw(RV_REG_S1, stack_adjust - 12, RV_REG_SP), ctx); in __build_epilogue()
158 emit(rv_lw(RV_REG_S2, stack_adjust - 16, RV_REG_SP), ctx); in __build_epilogue()
159 emit(rv_lw(RV_REG_S3, stack_adjust - 20, RV_REG_SP), ctx); in __build_epilogue()
160 emit(rv_lw(RV_REG_S4, stack_adjust - 24, RV_REG_SP), ctx); in __build_epilogue()
161 emit(rv_lw(RV_REG_S5, stack_adjust - 28, RV_REG_SP), ctx); in __build_epilogue()
162 emit(rv_lw(RV_REG_S6, stack_adjust - 32, RV_REG_SP), ctx); in __build_epilogue()
163 emit(rv_lw(RV_REG_S7, stack_adjust - 36, RV_REG_SP), ctx); in __build_epilogue()
165 emit(rv_addi(RV_REG_SP, RV_REG_SP, stack_adjust), ctx); in __build_epilogue()
[all …]
H A Dbpf_jit.h28 RV_REG_SP = 2, /* Stack pointer */ enumerator
672 return rv_ci_insn(0x3, imm, RV_REG_SP, 0x1); in rvc_addi16sp()
1020 if (rvc_enabled() && rd == RV_REG_SP && rd == rs && is_10b_int(imm) && imm && !(imm & 0xf)) in emit_addi()
1022 else if (rvc_enabled() && is_creg(rd) && rs == RV_REG_SP && is_10b_uint(imm) && in emit_addi()
1041 if (rvc_enabled() && rd && rd != RV_REG_SP && is_6b_int(imm) && imm) in emit_lui()
1113 if (rvc_enabled() && rs1 == RV_REG_SP && rd && is_8b_uint(off) && !(off & 0x3)) in emit_lw()
1123 if (rvc_enabled() && rs1 == RV_REG_SP && is_8b_uint(off) && !(off & 0x3)) in emit_sw()
1166 if (rvc_enabled() && rs1 == RV_REG_SP && rd && is_9b_uint(off) && !(off & 0x7)) in emit_ld()
1176 if (rvc_enabled() && rs1 == RV_REG_SP && is_9b_uint(off) && !(off & 0x7)) in emit_sd()