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Searched refs:RREG32_SOC15 (Results 1 – 25 of 114) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v4_3.c41 u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); in nbio_v4_3_get_rev_id()
61 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); in nbio_v4_3_get_memsize()
69 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL); in nbio_v4_3_sdma_doorbell_range()
108 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL); in nbio_v4_3_vcn_doorbell_range()
110 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL); in nbio_v4_3_vcn_doorbell_range()
184 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL); in nbio_v4_3_ih_doorbell_range()
223 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); in nbio_v4_3_ih_control()
246 def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); in nbio_v4_3_update_medium_grain_clock_gating()
276 def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); in nbio_v4_3_update_medium_grain_light_sleep()
293 data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); in nbio_v4_3_get_clockgating_state()
[all …]
H A Dimu_v12_0.c130 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); in imu_v12_0_wait_for_reset_status()
152 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); in imu_v12_0_setup()
156 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); in imu_v12_0_setup()
167 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); in imu_v12_0_start()
309 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in imu_v12_init_gfxhub_settings()
311 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_TOP); in imu_v12_init_gfxhub_settings()
313 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); in imu_v12_init_gfxhub_settings()
315 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE); in imu_v12_init_gfxhub_settings()
317 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT); in imu_v12_init_gfxhub_settings()
319 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP); in imu_v12_init_gfxhub_settings()
[all …]
H A Dnbio_v7_7.c42 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); in nbio_v7_7_get_rev_id()
61 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); in nbio_v7_7_get_memsize()
112 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN); in nbio_v7_7_enable_doorbell_aperture()
148 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, in nbio_v7_7_ih_doorbell_range()
176 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL); in nbio_v7_7_ih_control()
240 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3); in nbio_v7_7_init_registers()
251 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23); in nbio_v7_7_init_registers()
265 def = data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL); in nbio_v7_7_update_medium_grain_clock_gating()
294 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2); in nbio_v7_7_update_medium_grain_light_sleep()
303 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1); in nbio_v7_7_update_medium_grain_light_sleep()
[all …]
H A Dsmuio_v13_0.c48 def = data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); in smuio_v13_0_update_rom_clock_gating()
69 data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); in smuio_v13_0_get_clock_gating_state()
85 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_die_id()
102 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_socket_id()
119 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_is_host_gpu_xgmi_supported()
136 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_pkg_type()
H A Dumsch_mm_v4_0.c72 data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL); in umsch_mm_v4_0_load_microcode()
76 data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL); in umsch_mm_v4_0_load_microcode()
83 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_BASE_CNTL); in umsch_mm_v4_0_load_microcode()
129 data = RREG32_SOC15(VCN, 0, regUVD_UMSCH_FORCE); in umsch_mm_v4_0_load_microcode()
134 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL); in umsch_mm_v4_0_load_microcode()
139 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL); in umsch_mm_v4_0_load_microcode()
154 data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL); in umsch_mm_v4_0_load_microcode()
167 RREG32_SOC15(VCN, 0, regVCN_MES_MSTATUS_LO)); in umsch_mm_v4_0_load_microcode()
189 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL0); in umsch_mm_v4_0_aggregated_doorbell_init()
195 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL1); in umsch_mm_v4_0_aggregated_doorbell_init()
[all …]
H A Dmmhub_v2_3.c180 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_3_init_system_aperture_regs()
191 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_init_tlb_regs()
210 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_3_init_cache_regs()
223 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_3_init_cache_regs()
254 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_3_enable_system_domain()
387 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_gart_disable()
394 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_3_gart_disable()
411 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v2_3_set_fault_enable_default()
498 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL); in mmhub_v2_3_update_medium_grain_clock_gating()
499 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); in mmhub_v2_3_update_medium_grain_clock_gating()
[all …]
H A Dvcn_v4_0_5.c334 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v4_0_5_hw_fini()
620 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v4_0_5_disable_static_power_gating()
643 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v4_0_5_enable_static_power_gating()
688 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
694 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); in vcn_v4_0_5_disable_clock_gating()
719 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
742 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); in vcn_v4_0_5_disable_clock_gating()
769 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_5_disable_clock_gating()
859 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
865 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_5_enable_clock_gating()
[all …]
H A Dsmuio_v14_0_2.c45 clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in smuio_v14_0_2_get_gpu_clock_counter()
46 clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in smuio_v14_0_2_get_gpu_clock_counter()
48 clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in smuio_v14_0_2_get_gpu_clock_counter()
50 clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in smuio_v14_0_2_get_gpu_clock_counter()
H A Ddf_v1_7.c49 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v1_7_enable_broadcast_mode()
61 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
88 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
93 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
109 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_get_clockgating_state()
H A Dmmhub_v2_0.c252 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_0_init_system_aperture_regs()
263 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs()
288 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_init_cache_regs()
301 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_0_init_cache_regs()
332 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_0_enable_system_domain()
457 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_gart_disable()
464 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_gart_disable()
486 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v2_0_set_fault_enable_default()
578 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); in mmhub_v2_0_update_medium_grain_clock_gating()
581 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); in mmhub_v2_0_update_medium_grain_clock_gating()
[all …]
H A Dmmhub_v4_1_0.c198 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v4_1_0_init_system_aperture_regs()
209 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_init_tlb_regs()
235 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v4_1_0_init_cache_regs()
248 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v4_1_0_init_cache_regs()
279 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v4_1_0_enable_system_domain()
404 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_gart_disable()
411 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v4_1_0_gart_disable()
434 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v4_1_0_set_fault_enable_default()
524 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v4_1_0_get_fb_location()
534 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; in mmhub_v4_1_0_get_mc_fb_offset()
[all …]
H A Dmmhub_v3_0.c205 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_init_system_aperture_regs()
216 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_init_tlb_regs()
242 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_init_cache_regs()
255 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v3_0_init_cache_regs()
286 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v3_0_enable_system_domain()
411 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_gart_disable()
418 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_gart_disable()
440 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v3_0_set_fault_enable_default()
530 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v3_0_get_fb_location()
540 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; in mmhub_v3_0_get_mc_fb_offset()
[all …]
H A Dvcn_v5_0_0.c298 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v5_0_0_hw_fini()
587 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v5_0_0_disable_static_power_gating()
612 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v5_0_0_enable_static_power_gating()
709 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); in vcn_v5_0_0_start_dpg_mode()
770 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v5_0_0_start_dpg_mode()
777 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); in vcn_v5_0_0_start_dpg_mode()
779 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); in vcn_v5_0_0_start_dpg_mode()
781 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v5_0_0_start_dpg_mode()
793 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); in vcn_v5_0_0_start_dpg_mode()
829 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v5_0_0_start()
[all …]
H A Dmmhub_v1_0.c39 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); in mmhub_v1_0_get_fb_location()
40 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); in mmhub_v1_0_get_fb_location()
131 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_0_init_system_aperture_regs()
142 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
165 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_init_cache_regs()
176 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); in mmhub_v1_0_init_cache_regs()
203 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); in mmhub_v1_0_enable_system_domain()
262 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_CNTL); in mmhub_v1_0_init_saw()
272 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4); in mmhub_v1_0_init_saw()
402 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_gart_disable()
[all …]
H A Dhdp_v5_0.c53 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_mem_power_gating()
54 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_update_mem_power_gating()
144 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_medium_grain_clock_gating()
180 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_get_clockgating_state()
190 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_get_clockgating_state()
203 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); in hdp_v5_0_init_registers()
H A Dgfx_v11_0.c982 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
995 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_regs()
1990 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1994 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
2009 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
2013 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
2082 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); in gfx_v11_0_init_compute_vmid()
2127 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | in gfx_v11_0_get_tcc_info()
2128 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); in gfx_v11_0_get_tcc_info()
2149 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); in gfx_v11_0_constants_init()
[all …]
H A Dmmhub_v3_0_1.c211 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_1_init_system_aperture_regs()
222 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_init_tlb_regs()
242 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_1_init_cache_regs()
255 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v3_0_1_init_cache_regs()
286 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v3_0_1_enable_system_domain()
405 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_gart_disable()
412 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_1_gart_disable()
429 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v3_0_1_set_fault_enable_default()
513 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v3_0_1_get_fb_location()
522 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; in mmhub_v3_0_1_get_mc_fb_offset()
[all …]
H A Dgfxhub_v1_1.c53 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE); in gfxhub_v1_1_get_xgmi_info()
55 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE), in gfxhub_v1_1_get_xgmi_info()
60 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); in gfxhub_v1_1_get_xgmi_info()
62 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), in gfxhub_v1_1_get_xgmi_info()
H A Dnbio_v2_3.c86 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); in nbio_v2_3_get_rev_id()
105 return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); in nbio_v2_3_get_memsize()
189 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); in nbio_v2_3_ih_doorbell_range()
213 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); in nbio_v2_3_ih_control()
386 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2); in nbio_v2_3_program_ltr()
430 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); in nbio_v2_3_program_aspm()
436 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5); in nbio_v2_3_program_aspm()
466 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); in nbio_v2_3_program_aspm()
472 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5); in nbio_v2_3_program_aspm()
538 reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL); in nbio_v2_3_clear_doorbell_interrupt()
[all …]
H A Dnbio_v7_4.c114 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE); in nbio_v7_4_get_rev_id()
116 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); in nbio_v7_4_get_rev_id()
135 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); in nbio_v7_4_get_memsize()
236 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); in nbio_v7_4_ih_doorbell_range()
296 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); in nbio_v7_4_ih_control()
347 baco_cntl = RREG32_SOC15(NBIO, 0, mmBACO_CNTL); in nbio_v7_4_init_registers()
370 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
372 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
427 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE); in nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring()
429 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); in nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring()
[all …]
H A Djpeg_v5_0_0.c194 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) in jpeg_v5_0_0_hw_fini()
246 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); in jpeg_v5_0_0_disable_clock_gating()
256 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); in jpeg_v5_0_0_enable_clock_gating()
261 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); in jpeg_v5_0_0_enable_clock_gating()
349 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v5_0_0_start_dpg_mode()
396 ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR); in jpeg_v5_0_0_start_dpg_mode()
413 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v5_0_0_stop_dpg_mode()
473 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); in jpeg_v5_0_0_start()
523 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); in jpeg_v5_0_0_dec_ring_get_rptr()
540 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); in jpeg_v5_0_0_dec_ring_get_wptr()
[all …]
H A Dhdp_v5_2.c65 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_mem_power_gating()
66 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_update_mem_power_gating()
147 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_medium_grain_clock_gating()
176 tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_get_clockgating_state()
186 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_get_clockgating_state()
H A Djpeg_v4_0_5.c260 RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS)) in jpeg_v4_0_5_hw_fini()
311 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL); in jpeg_v4_0_5_disable_clock_gating()
323 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE); in jpeg_v4_0_5_disable_clock_gating()
335 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL); in jpeg_v4_0_5_enable_clock_gating()
347 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE); in jpeg_v4_0_5_enable_clock_gating()
427 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v4_0_5_start_dpg_mode()
440 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v4_0_5_start_dpg_mode()
473 ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_5_start_dpg_mode()
488 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v4_0_5_stop_dpg_mode()
558 ring->wptr = RREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_5_start()
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_thermal.c74 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_get_fan_speed_pwm()
76 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), in vega10_fan_ctrl_get_fan_speed_pwm()
104 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
132 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
135 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
141 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
144 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
161 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
165 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
263 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_set_fan_speed_pwm()
[all …]
H A Dvega20_thermal.c95 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega20_fan_ctrl_set_static_mode()
98 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega20_fan_ctrl_set_static_mode()
124 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_get_fan_speed_pwm()
126 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), in vega20_fan_ctrl_get_fan_speed_pwm()
152 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_set_fan_speed_pwm()
163 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), in vega20_fan_ctrl_set_fan_speed_pwm()
206 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), in vega20_fan_ctrl_set_fan_speed_rpm()
223 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); in vega20_thermal_get_temperature()
260 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); in vega20_thermal_set_temperature_range()

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