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Searched refs:REG_FIELD_GET (Results 1 – 25 of 52) sorted by relevance

123

/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_fw.c110 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val); in guc_load_done()
111 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, val); in guc_load_done()
207 REG_FIELD_GET(GS_BOOTROM_MASK, status), in guc_wait_ucode()
208 REG_FIELD_GET(GS_UKERNEL_MASK, status)); in guc_wait_ucode()
214 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); in guc_wait_ucode()
215 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); in guc_wait_ucode()
220 REG_FIELD_GET(GS_MIA_IN_RESET, status), in guc_wait_ucode()
222 REG_FIELD_GET(GS_MIA_MASK, status), in guc_wait_ucode()
223 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); in guc_wait_ucode()
H A Dintel_gsc_fw.c21 return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fw_status) == in gsc_is_in_reset()
42 return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, in intel_gsc_uc_fw_proxy_init_done()
/linux/drivers/gpu/drm/xe/
H A Dxe_gt_topology.c157 u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3); in load_l3_bank_mask()
159 u32 bank_val = REG_FIELD_GET(XE3_L3BANK_ENABLE, mirror_l3bank_enable); in load_l3_bank_mask()
166 u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3); in load_l3_bank_mask()
167 u32 bank_val = REG_FIELD_GET(XE2_GT_L3_MODE_MASK, fuse3); in load_l3_bank_mask()
175 u32 meml3_en = REG_FIELD_GET(MEML3_EN_MASK, fuse3); in load_l3_bank_mask()
177 u32 bank_val = REG_FIELD_GET(GT_L3_EXC_MASK, fuse4); in load_l3_bank_mask()
186 u32 meml3_en = REG_FIELD_GET(MEML3_EN_MASK, fuse3); in load_l3_bank_mask()
187 u32 bank_val = REG_FIELD_GET(XEHPC_GT_L3_MODE_MASK, fuse3); in load_l3_bank_mask()
196 u32 mask = REG_FIELD_GET(MEML3_EN_MASK, fuse3); in load_l3_bank_mask()
202 u32 mask = REG_FIELD_GET(XELP_GT_L3_MODE_MASK, ~fuse3); in load_l3_bank_mask()
H A Dxe_hwmon.c354 reg_val = REG_FIELD_GET(PWR_LIM_VAL, reg_val); in xe_hwmon_power_max_read()
362 min = REG_FIELD_GET(PKG_MIN_PWR, pkg_pwr); in xe_hwmon_power_max_read()
363 max = REG_FIELD_GET(PKG_MAX_PWR, pkg_pwr); in xe_hwmon_power_max_read()
468 reg_val = REG_FIELD_GET(PKG_TDP, reg_val); in xe_hwmon_power_rated_max_read()
566 x = REG_FIELD_GET(PWR_LIM_TIME_X, reg_val); in xe_hwmon_power_max_interval_show()
567 y = REG_FIELD_GET(PWR_LIM_TIME_Y, reg_val); in xe_hwmon_power_max_interval_show()
620 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); in xe_hwmon_power_max_interval_store()
621 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); in xe_hwmon_power_max_interval_store()
775 hwmon->temp.count = REG_FIELD_GET(TEMP_MASK, config); in xe_hwmon_pcode_read_thermal_info()
816 data = REG_FIELD_GET(PCIE_SENSOR_MASK, data); in get_pcie_temp()
[all …]
H A Dxe_guc.c1016 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); in print_load_status_err()
1017 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); in print_load_status_err()
1020 REG_FIELD_GET(GS_MIA_IN_RESET, status), in print_load_status_err()
1022 REG_FIELD_GET(GS_MIA_MASK, status), in print_load_status_err()
1023 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); in print_load_status_err()
1073 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, *status); in guc_load_done()
1074 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, *status); in guc_load_done()
1703 REG_FIELD_GET(GS_BOOTROM_MASK, status)); in xe_guc_print_info()
1705 REG_FIELD_GET(GS_UKERNEL_MASK, status)); in xe_guc_print_info()
1707 REG_FIELD_GET(GS_MIA_MASK, status)); in xe_guc_print_info()
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H A Dxe_hw_engine.c592 idledly = REG_FIELD_GET(IDLE_DELAY, idledly); in adjust_idledly()
594 maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt); in adjust_idledly()
696 vdbox_mask = REG_FIELD_GET(GT_VDBOX_DISABLE_MASK, media_fuse); in read_media_fuses()
697 vebox_mask = REG_FIELD_GET(GT_VEBOX_DISABLE_MASK, media_fuse); in read_media_fuses()
722 u32 meml3 = REG_FIELD_GET(MEML3_EN_MASK, in infer_svccopy_from_meml3()
738 return REG_FIELD_GET(FUSE_SERVICE_COPY_ENABLE_MASK, in read_svccopy_fuses()
800 ccs_mask = REG_FIELD_GET(CCS_EN_MASK, ccs_mask); in read_compute_fuses_from_reg()
H A Dxe_lrc.c1853 return REG_FIELD_GET(CMD_3DSTATE_SO_DECL_LIST_DW_LEN, cmd_header) + 2; in instr_dw()
1856 return REG_FIELD_GET(XE_INSTR_LEN_MASK, cmd_header) + 2; in instr_dw()
1866 u32 opcode = REG_FIELD_GET(MI_OPCODE, inst_header); in dump_mi_command()
1935 u32 pipeline = REG_FIELD_GET(GFXPIPE_PIPELINE, *dw); in dump_gfxpipe_command()
1936 u32 opcode = REG_FIELD_GET(GFXPIPE_OPCODE, *dw); in dump_gfxpipe_command()
1937 u32 subopcode = REG_FIELD_GET(GFXPIPE_SUBOPCODE, *dw); in dump_gfxpipe_command()
2087 u32 opcode = REG_FIELD_GET(GFX_STATE_OPCODE, *dw); in dump_gfx_state_command()
2135 *dw, REG_FIELD_GET(XE_INSTR_CMD_TYPE, *dw), in xe_lrc_dump_default()
2388 u16 class = REG_FIELD_GET(ENGINE_CLASS_ID, engine_id); in get_ctx_timestamp()
2389 u16 instance = REG_FIELD_GET(ENGINE_INSTANCE_ID, engine_id); in get_ctx_timestamp()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_vdsc.c926 vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp); in intel_dsc_get_pps_config()
927 vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp); in intel_dsc_get_pps_config()
938 vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp); in intel_dsc_get_pps_config()
948 vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances; in intel_dsc_get_pps_config()
949 vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp); in intel_dsc_get_pps_config()
954 vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp); in intel_dsc_get_pps_config()
955 vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp); in intel_dsc_get_pps_config()
960 vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp); in intel_dsc_get_pps_config()
961 vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp); in intel_dsc_get_pps_config()
966 vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp); in intel_dsc_get_pps_config()
[all …]
H A Dintel_pmdemand.c423 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
425 REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
427 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
429 REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
432 REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
434 REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
438 REG_FIELD_GET(XE3_PMDEMAND_PIPES_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
441 REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
443 REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
446 REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
[all …]
H A Dintel_lvds.c96 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val); in intel_lvds_port_enabled()
98 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val); in intel_lvds_port_enabled()
166 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
167 pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
168 pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
171 pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
172 pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
175 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
176 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
H A Dintel_color.c840 entry->red = intel_color_lut_pack(REG_FIELD_GET(PALETTE_RED_MASK, val), 8); in i9xx_lut_8_pack()
841 entry->green = intel_color_lut_pack(REG_FIELD_GET(PALETTE_GREEN_MASK, val), 8); in i9xx_lut_8_pack()
842 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PALETTE_BLUE_MASK, val), 8); in i9xx_lut_8_pack()
889 u16 red = REG_FIELD_GET(PALETTE_10BIT_RED_LDW_MASK, ldw) | in i9xx_lut_10_pack()
890 REG_FIELD_GET(PALETTE_10BIT_RED_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
891 u16 green = REG_FIELD_GET(PALETTE_10BIT_GREEN_LDW_MASK, ldw) | in i9xx_lut_10_pack()
892 REG_FIELD_GET(PALETTE_10BIT_GREEN_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
893 u16 blue = REG_FIELD_GET(PALETTE_10BIT_BLUE_LDW_MASK, ldw) | in i9xx_lut_10_pack()
894 REG_FIELD_GET(PALETTE_10BIT_BLUE_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
904 int r_exp = REG_FIELD_GET(PALETTE_10BIT_RED_EXP_MASK, udw); in i9xx_lut_10_pack_slope()
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H A Dintel_flipq.c247 REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, tmp), in intel_flipq_dump()
248 REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, tmp), in intel_flipq_dump()
249 REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, tmp), in intel_flipq_dump()
250 REG_FIELD_GET(PIPEDMC_FPQ_GENERALQ_TP_MASK, tmp), in intel_flipq_dump()
251 REG_FIELD_GET(PIPEDMC_FPQ_FASTQ_TP_MASK, tmp)); in intel_flipq_dump()
H A Dintel_casf.c148 REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16)) in intel_casf_sharpness_get_config()
152 REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp); in intel_casf_sharpness_get_config()
155 REG_FIELD_GET(FILTER_SIZE_MASK, sharp); in intel_casf_sharpness_get_config()
H A Dintel_pfit.c631 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl); in ilk_pfit_get_config()
641 REG_FIELD_GET(PF_WIN_XPOS_MASK, pos), in ilk_pfit_get_config()
642 REG_FIELD_GET(PF_WIN_YPOS_MASK, pos), in ilk_pfit_get_config()
643 REG_FIELD_GET(PF_WIN_XSIZE_MASK, size), in ilk_pfit_get_config()
644 REG_FIELD_GET(PF_WIN_YSIZE_MASK, size)); in ilk_pfit_get_config()
721 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp); in i9xx_pfit_get_config()
H A Dintel_bw.c82 dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val); in dg1_mchbar_read_qgv_point_info()
97 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); in dg1_mchbar_read_qgv_point_info()
98 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); in dg1_mchbar_read_qgv_point_info()
101 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val); in dg1_mchbar_read_qgv_point_info()
102 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val); in dg1_mchbar_read_qgv_point_info()
220 dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); in mtl_read_qgv_point_info()
222 sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); in mtl_read_qgv_point_info()
223 sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); in mtl_read_qgv_point_info()
225 sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2); in mtl_read_qgv_point_info()
226 sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2); in mtl_read_qgv_point_info()
H A Dintel_crt.c100 *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val); in intel_crt_port_enabled()
102 *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val); in intel_crt_port_enabled()
717 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1; in intel_crt_load_detect()
718 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1; in intel_crt_load_detect()
720 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1; in intel_crt_load_detect()
721 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; in intel_crt_load_detect()
757 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; in intel_crt_load_detect()
H A Dintel_hti.c42 return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, display->hti.state); in intel_hti_dpll_mask()
H A Dskl_watermark.c113 return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); in intel_sagv_block_time()
673 REG_FIELD_GET(PLANE_BUF_START_MASK, reg), in skl_ddb_entry_init_from_hw()
674 REG_FIELD_GET(PLANE_BUF_END_MASK, reg)); in skl_ddb_entry_init_from_hw()
702 *min_ddb = REG_FIELD_GET(PLANE_MIN_DBUF_BLOCKS_MASK, val); in skl_ddb_get_hw_plane_state()
703 *interim_ddb = REG_FIELD_GET(PLANE_INTERIM_DBUF_BLOCKS_MASK, val); in skl_ddb_get_hw_plane_state()
2890 latency = REG_FIELD_GET(LNL_PKG_C_LATENCY_MASK, in intel_program_dpkgc_latency()
2971 level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val); in skl_wm_level_from_reg_val()
2972 level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); in skl_wm_level_from_reg_val()
3266 wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
3267 wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); in mtl_read_wm_latency()
[all …]
H A Dintel_vrr.c1034 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); in intel_vrr_get_config()
1038 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); in intel_vrr_get_config()
1078 REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync); in intel_vrr_get_config()
1080 REG_FIELD_GET(VRR_VSYNC_END_MASK, trans_vrr_vsync); in intel_vrr_get_config()
1151 if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0) in intel_vrr_dcb_vmin_vblank_start_next()
1165 if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0) in intel_vrr_dcb_vmax_vblank_start_next()
H A Dintel_snps_phy.c1930 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1; in intel_mpllb_calc_port_clock()
1932 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1); in intel_mpllb_calc_port_clock()
1935 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2); in intel_mpllb_calc_port_clock()
1936 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2); in intel_mpllb_calc_port_clock()
1937 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1); in intel_mpllb_calc_port_clock()
1940 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16; in intel_mpllb_calc_port_clock()
1942 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div); in intel_mpllb_calc_port_clock()
H A Dskl_scaler.c997 REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), in skl_scaler_get_config()
998 REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), in skl_scaler_get_config()
999 REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), in skl_scaler_get_config()
1000 REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); in skl_scaler_get_config()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.c241 eu_en_fuse = REG_FIELD_GET(XEHP_EU_ENA_MASK, in xehp_sseu_info_init()
275 s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK, in gen12_sseu_info_init()
282 eu_en_fuse = ~REG_FIELD_GET(GEN11_EU_DIS_MASK, in gen12_sseu_info_init()
312 s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK, in gen11_sseu_info_init()
318 eu_en = ~REG_FIELD_GET(GEN11_EU_DIS_MASK, in gen11_sseu_info_init()
341 REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R0_MASK, fuse) | in cherryview_sseu_info_init()
342 REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS0_R0_MASK); in cherryview_sseu_info_init()
350 REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R0_MASK, fuse) | in cherryview_sseu_info_init()
351 REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS1_R0_MASK); in cherryview_sseu_info_init()
387 sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2); in gen9_sseu_info_init()
[all …]
H A Dintel_gt_mcr.c125 gt->info.mslice_mask |= REG_FIELD_GET(GEN12_MEML3_EN_MASK, in intel_gt_mcr_init()
138 fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK, in intel_gt_mcr_init()
142 fuse = REG_FIELD_GET(GT_L3_EXC_MASK, in intel_gt_mcr_init()
/linux/drivers/gpu/drm/i915/
H A Di915_hwmon.c110 reg_value = REG_FIELD_GET(field_msk, reg_value); in hwm_field_read_and_scale()
180 x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r); in hwm_power1_max_interval_show()
181 y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r); in hwm_power1_max_interval_show()
224 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); in hwm_power1_max_interval_store()
225 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); in hwm_power1_max_interval_store()
340 *val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE; in hwm_temp_read()
372 *val = DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) * 25, 10); in hwm_in_read()
430 min = REG_FIELD_GET(PKG_MIN_PWR, r); in hwm_power_max_read()
432 max = REG_FIELD_GET(PKG_MAX_PWR, r); in hwm_power_max_read()
520 *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), in hwm_power_read()
[all …]
H A Dintel_device_info.c312 ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); in ip_ver_read()
313 ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); in ip_ver_read()
314 ip->step = REG_FIELD_GET(GMD_ID_STEP, val); in ip_ver_read()

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