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Searched refs:REG_CLR (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/thermal/
H A Dimx91_thermal.c21 #define REG_CLR 0x8 macro
92 reg += enable ? REG_SET : REG_CLR; in imx91_tmu_enable()
127 writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_CLR); in imx91_tmu_set_trips()
130 writel_relaxed(IMX91_TMU_THR_CTRL01_THR1_MASK, tmu->base + IMX91_TMU_THR_CTRL01 + REG_CLR); in imx91_tmu_set_trips()
135 writel_relaxed(IMX91_TMU_STAT0_THR1_IF, tmu->base + IMX91_TMU_STAT0 + REG_CLR); in imx91_tmu_set_trips()
183 writel(IMX91_TMU_STAT0_THR1_IF, tmu->base + IMX91_TMU_STAT0 + REG_CLR); in imx91_tmu_alarm_irq()
184 writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_CLR); in imx91_tmu_alarm_irq()
212 tmu->base + IMX91_TMU_CTRL0 + REG_CLR); in imx91_tmu_change_mode()
218 writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_CLR); in imx91_tmu_change_mode()
289 tmu->base + IMX91_TMU_CTRL1 + REG_CLR); in imx91_tmu_probe()
[all …]
H A Dimx_thermal.c21 #define REG_CLR 0x8 macro
228 regmap_write(map, soc_data->panic_alarm_ctrl + REG_CLR, in imx_set_panic_temp()
248 regmap_write(map, soc_data->high_alarm_ctrl + REG_CLR, in imx_set_alarm_temp()
615 regmap_write(map, IMX6_MISC1 + REG_CLR, in imx_thermal_probe()
646 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe()
648 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe()
650 regmap_write(map, data->socdata->measure_freq_ctrl + REG_CLR, in imx_thermal_probe()
702 regmap_write(map, data->socdata->measure_freq_ctrl + REG_CLR, in imx_thermal_probe()
712 regmap_write(map, data->socdata->sensor_ctrl + REG_CLR, in imx_thermal_probe()
806 ret = regmap_write(map, socdata->sensor_ctrl + REG_CLR, in imx_thermal_runtime_suspend()
[all …]
/linux/arch/arm/mach-imx/
H A Danatop.c17 #define REG_CLR 0x8 macro
46 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
/linux/drivers/gpu/drm/mxsfb/
H A Dmxsfb_kms.c216 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR); in mxsfb_disable_controller()
239 writel(mask, addr + REG_CLR); in clear_poll_bit()
257 writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR); in mxsfb_reset_block()
270 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_reset_block()
429 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_enable_vblank()
440 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_disable_vblank()
441 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_disable_vblank()
H A Dmxsfb_drv.c173 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_handler()
185 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
186 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
H A Dmxsfb_regs.h13 #define REG_CLR 8 macro
H A Dlcdif_regs.h12 #define REG_CLR 8 macro
H A Dlcdif_kms.c398 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_CLR); in lcdif_reset_block()
/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-lvds-phy.c19 #define REG_CLR 0x8 macro
154 regmap_write(priv->regmap, PHY_CTRL + REG_CLR, in mixel_lvds_phy_power_off()
157 regmap_write(priv->regmap, PHY_CTRL + REG_CLR, in mixel_lvds_phy_power_off()
/linux/drivers/misc/rp1/
H A Drp1_pci.c22 #define REG_CLR 0xc00 macro
52 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_CLR + MSIX_CFG(hwirq)); in msix_cfg_clr()